9.6.1.18 DIG_VOL_CTRL3 Register (Offset = 4Fh) [reset = 0x30]
DIG_VOL_CTRL3 is shown in Figure 99 and described in Table 24.
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Figure 99. DIG_VOL_CTRL3 Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
FAST_RAMP_DOWN_SPEED |
FAST_RAMP_DOWN_STEP |
RESERVED |
R/W |
R/W |
R/W |
|
Table 24. DIG_VOL_CTRL3 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-6 |
FAST_RAMP_DOWN_SPEED |
R/W |
00 |
Digital Volume Emergency Ramp Down Frequency
These bits control the frequency of the digital volume updates when the volume is ramping down due to clock error or power outage, which usually needs faster ramp down compared to normal soft mute.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly set the volume to zero (Instant mute) |
5-4 |
FAST_RAMP_DOWN_STEP |
R/W |
11 |
Digital Volume Emergency Ramp Down Step
These bits control the step of the digital volume updates when the volume is ramping down due to clock error or power outage, which usually needs faster ramp down compared to normal soft mute.
00: Decrement by 4 dB for each update
01: Decrement by 2 dB for each update
10: Decrement by 1 dB for each update
11: Decrement by 0.5 dB for each update |
3-0 |
RESERVED |
R/W |
0000 |
This bit is reserved
|