9.6.1.8 I2S_CTRL Register (Offset = 31h) [reset = 0x00]
I2S_CTRL is shown in Figure 89 and described in Table 14.
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Figure 89. I2S_CTRL Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
BCK_INV |
RESERVED |
RESERVED |
RESERVED |
R/W |
R/W |
R/W |
R |
R |
R/W |
|
Table 14. I2S_CTRL Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-6 |
RESERVED |
R/W |
00 |
This bit is reserved
|
5 |
BCK_INV |
R/W |
0 |
BCK Polarity
This bit sets the inverted BCK mode. In inverted BCK mode, the DAC assumes that the LRCK and DIN edges are aligned to the rising edge of the BCK. Normally they are assumed to be aligned to the falling edge of the BCK.
0: Normal BCK mode
1: Inverted BCK mode |
4-0 |
RESERVED |
R/W |
00000 |
This bit is reserved
|