9.6.1.42 PIN_CONTROL2 Register (Offset = 75h) [reset = 0xF8]
PIN_CONTROL2 is shown in Figure 123 and described in Table 48.
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Figure 123. PIN_CONTROL2 Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
CLKFLT_LATCH_EN |
OTSD_LATCH_EN |
OTW_LATCH_EN |
MASK_OTW |
RESERVED |
|
R/W |
R/W |
R/W |
R/W |
|
|
Table 48. PIN_CONTROL2 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-6 |
RESERVED |
R/W |
11 |
This bit is reserved
|
5 |
CLKFLT_LATCH_EN |
R/W |
1 |
Enable clock fault latch
|
4 |
OTSD_LATCH_EN |
R/W |
1 |
Enable OTSD fault latch
|
3 |
OTW_LATCH_EN |
R/W |
1 |
Enable OT warning latch
|
2 |
MASK_OTW |
R/W |
0 |
Mask OT warning report
|
1-0 |
RESERVED |
R/W |
00 |
This bit is reserved
|