9.6.1.9 SAP_CTRL1 Register (Offset = 33h) [reset = 0x02]
SAP_CTRL1 is shown in Figure 90 and described in Table 15.
Return to Summary Table.
Figure 90. SAP_CTRL1 Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
I2S_SHIFT_MSB |
RESERVED |
DATA_FORMAT |
I2S_LRCLK_PULSE |
WORD_LENGTH |
R/W |
R/W |
R/W |
R/W |
R/W |
|
Table 15. SAP_CTRL1 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7 |
I2S_SHIFT_MSB |
R/W |
0 |
I2S Shift MSB
|
6 |
RESERVED |
R/W |
0 |
This bit is reserved
|
5-4 |
DATA_FORMAT |
R/W |
00 |
I2S Data Format
These bits control both input and output audio interface formats for DAC operation.
00: I2S
01: TDM/DSP
10: RTJ
11: LTJ |
3-2 |
I2S_LRCLK_PULSE |
R/W |
00 |
01: lrclk pulse < 8 SCLK. If the high width of LRCLK/FS in TDM/DSP mode is less than 8 cycles of SCK, these two bits need set to 01.
|
1-0 |
WORD_LENGTH |
R/W |
10 |
I2S Word Length
These bits control both input and output audio interface sample word lengths for DAC operation.
00: 16 bits
01: 20 bits
10: 24 bits
11: 32 bits |