SLASEO2 May 2019 TAS5806MD
PRODUCTION DATA.
SS_CTRL0 is shown in Figure 113 and described in Table 38.
Return to Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | SS_PRE_DIV_SEL | SS_MANUAL_MODE | RESERVED | SS_RDM_EN | SS_TRI_EN | |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R/W | 0 |
This bit is reserved |
6 | RESERVED | R/W | 0 |
This bit is reserved |
5 | SS_PRE_DIV_SEL | R/W | 0 |
Select pll clock divide 2 as source clock in manual mode |
4 | SS_MANUAL_MODE | R/W | 0 |
Set ramp ss controller to manual mode |
3-2 | RESERVED | R/W | 0 |
This bit is reserved |
1 | SS_RDM_EN | R/W | 0 |
Random SS enable |
0 | SS_TRI_EN | R/W | 0 |
Triangle SS enable |