9.6.1.33 SS_CTRL1 Register (Offset = 6Ch) [reset = 0x00]
SS_CTRL1 is shown in Figure 114 and described in Table 39.
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Figure 114. SS_CTRL1 Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
SS_RDM_CTRL |
SS_TRI_CTRL |
R/W |
R/W |
R/W |
|
Table 39. SS_CTRL1 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7 |
RESERVED |
R/W |
0 |
This bit is reserved
|
6-4 |
SS_RDM_CTRL |
R/W |
000 |
Random SS range control
|
3-0 |
SS_TRI_CTRL |
R/W |
0000 |
Triangle SS frequency and range control
|