SLASEH7H October   2019  – January 2023 TAS5825M

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
      1. 7.7.1 Bridge Tied Load (BTL) Configuration Curves with Hybrid Modulation
      2. 7.7.2 Parallel Bridge Tied Load (PBTL) Configuration With Hybrid Modulation
      3. 7.7.3 Bridge Tied Load (BTL) Configuration Curves with BD Modulation
      4. 7.7.4 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power Supplies
      2. 9.3.2 Device Clocking
      3. 9.3.3 Serial Audio Port – Clock Rates
      4. 9.3.4 Clock Halt Auto-Recovery
      5. 9.3.5 Sample Rate on the Fly Change
      6. 9.3.6 Serial Audio Port - Data Formats and Bit Depths
      7. 9.3.7 Digital Audio Processing
      8. 9.3.8 Class D Audio Amplifier
        1. 9.3.8.1 Speaker Amplifier Gain Select
        2. 9.3.8.2 Class D Loop Bandwidth and Switching Frequency Setting
    4. 9.4 Device Functional Modes
      1. 9.4.1 Software Control
      2. 9.4.2 Speaker Amplifier Operating Modes
        1. 9.4.2.1 BTL Mode
        2. 9.4.2.2 PBTL Mode
      3. 9.4.3 Low EMI Modes
        1. 9.4.3.1 Spread Spectrum
        2. 9.4.3.2 Channel to Channel Phase Shift
        3. 9.4.3.3 Multi-Devices PWM Phase Synchronization
          1. 9.4.3.3.1 Phase Synchronization With I2S Clock In Startup Phase
          2. 9.4.3.3.2 Phase Synchronization With GPIO
      4. 9.4.4 Thermal Foldback
      5. 9.4.5 Device State Control
      6. 9.4.6 Device Modulation
        1. 9.4.6.1 BD Modulation
        2. 9.4.6.2 1SPW Modulation
        3. 9.4.6.3 Hybrid Modulation
    5. 9.5 Programming and Control
      1. 9.5.1 I2 C Serial Communication Bus
      2. 9.5.2 I2 C Target Address
        1. 9.5.2.1 Random Write
        2. 9.5.2.2 Sequential Write
        3. 9.5.2.3 Random Read
        4. 9.5.2.4 Sequential Read
        5. 9.5.2.5 DSP Memory Book, Page and BQ update
        6. 9.5.2.6 Checksum
          1. 9.5.2.6.1 Cyclic Redundancy Check (CRC) Checksum
          2. 9.5.2.6.2 Exclusive or (XOR) Checksum
      3. 9.5.3 Control via Software
        1. 9.5.3.1 Startup Procedures
        2. 9.5.3.2 Shutdown Procedures
        3. 9.5.3.3 Protection and Monitoring
          1. 9.5.3.3.1 Overcurrent Limit (Cycle-By-Cycle)
          2. 9.5.3.3.2 Overcurrent Shutdown (OCSD)
          3. 9.5.3.3.3 DC Detect
    6. 9.6 Register Maps
      1. 9.6.1 CONTROL PORT Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Inductor Selections
      2. 10.1.2 Bootstrap Capacitors
      3. 10.1.3 Power Supply Decoupling
      4. 10.1.4 Output EMI Filtering
    2. 10.2 Typical Applications
      1. 10.2.1 2.0 (Stereo BTL) System
      2. 10.2.2 Design Requirements
      3. 10.2.3 Detailed Design procedures
        1. 10.2.3.1 Step One: Hardware Integration
        2. 10.2.3.2 Step Two: Hardware Integration
        3. 10.2.3.3 Step Three: Software Integration
      4. 10.2.4 Application Curves
      5. 10.2.5 MONO (PBTL) Systems
      6. 10.2.6 Advanced 2.1 System (Two TAS5825M Devices)
      7. 10.2.7 Application Curves
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 DVDD Supply
      2. 10.3.2 PVDD Supply
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
        1. 10.4.1.1 General Guidelines for Audio Amplifiers
        2. 10.4.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
        3. 10.4.1.3 Optimizing Thermal Performance
          1. 10.4.1.3.1 Device, Copper, and Component Layout
          2. 10.4.1.3.2 Stencil Pattern
            1. 10.4.1.3.2.1 PCB footprint and Via Arrangement
            2. 10.4.1.3.2.2 Solder Stencil
      2. 10.4.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Development Support
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
10.4.1.3.2.1 PCB footprint and Via Arrangement

The PCB footprint (also known as a symbol or land pattern) communicates to the PCB fabrication vendor the shape and position of the copper patterns to which the TAS5825M device is soldered. This footprint can be followed directly from the guidance in the package addendum at the end of this data sheet. TI recommends to make sure that the thermal pad, which connects electrically and thermally to the PowerPAD™ of the TAS5825M device, be made no smaller than what is specified in the package addendum. This method makes sure that the TAS5825M device has the largest interface possible to move heat from the device to the board.

The via pattern shown in the package addendum provides an improved interface to carry the heat from the device through to the layers of the PCB, because small diameter plated vias (with minimally-sized annular rings) present a low thermal-impedance path from the device into the PCB. Once into the PCB, the heat travels away from the device and into the surrounding structures and air. By increasing the number of vias, as shown in Section 10.4.2, this interface can benefit from improved thermal performance.

Note:

Vias can obstruct heat flow if the vias are not constructed properly.

More notes on the construction and placement of vias are as follows:

  • Remove thermal reliefs on thermal vias, because the thermal reliefs impede the flow of heat through the via.
  • Vias filled with thermally conductive material are best, but a simple plated via can be used to avoid the additional cost of filled vias.
  • The diameter of the drill must be 8 mm or less. Also, the distance between the via barrel and the surrounding planes must be minimized to help heat flow from the via into the surrounding copper material. In all cases, minimum spacing must be determined by the voltages present on the planes surrounding the via and minimized wherever possible.
  • Vias must be arranged in columns, which extend in a line radially from the heat source to the surrounding area. This arrangement is shown in Section 10.4.2.
  • Make sure that vias do not cut off power current flow from the power supply through the planes on internal layers. If needed, remove some vias that are farthest from the TAS5825M device to open up the current path to and from the device.