SLASEH7H October   2019  – January 2023 TAS5825M

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
      1. 7.7.1 Bridge Tied Load (BTL) Configuration Curves with Hybrid Modulation
      2. 7.7.2 Parallel Bridge Tied Load (PBTL) Configuration With Hybrid Modulation
      3. 7.7.3 Bridge Tied Load (BTL) Configuration Curves with BD Modulation
      4. 7.7.4 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power Supplies
      2. 9.3.2 Device Clocking
      3. 9.3.3 Serial Audio Port – Clock Rates
      4. 9.3.4 Clock Halt Auto-Recovery
      5. 9.3.5 Sample Rate on the Fly Change
      6. 9.3.6 Serial Audio Port - Data Formats and Bit Depths
      7. 9.3.7 Digital Audio Processing
      8. 9.3.8 Class D Audio Amplifier
        1. 9.3.8.1 Speaker Amplifier Gain Select
        2. 9.3.8.2 Class D Loop Bandwidth and Switching Frequency Setting
    4. 9.4 Device Functional Modes
      1. 9.4.1 Software Control
      2. 9.4.2 Speaker Amplifier Operating Modes
        1. 9.4.2.1 BTL Mode
        2. 9.4.2.2 PBTL Mode
      3. 9.4.3 Low EMI Modes
        1. 9.4.3.1 Spread Spectrum
        2. 9.4.3.2 Channel to Channel Phase Shift
        3. 9.4.3.3 Multi-Devices PWM Phase Synchronization
          1. 9.4.3.3.1 Phase Synchronization With I2S Clock In Startup Phase
          2. 9.4.3.3.2 Phase Synchronization With GPIO
      4. 9.4.4 Thermal Foldback
      5. 9.4.5 Device State Control
      6. 9.4.6 Device Modulation
        1. 9.4.6.1 BD Modulation
        2. 9.4.6.2 1SPW Modulation
        3. 9.4.6.3 Hybrid Modulation
    5. 9.5 Programming and Control
      1. 9.5.1 I2 C Serial Communication Bus
      2. 9.5.2 I2 C Target Address
        1. 9.5.2.1 Random Write
        2. 9.5.2.2 Sequential Write
        3. 9.5.2.3 Random Read
        4. 9.5.2.4 Sequential Read
        5. 9.5.2.5 DSP Memory Book, Page and BQ update
        6. 9.5.2.6 Checksum
          1. 9.5.2.6.1 Cyclic Redundancy Check (CRC) Checksum
          2. 9.5.2.6.2 Exclusive or (XOR) Checksum
      3. 9.5.3 Control via Software
        1. 9.5.3.1 Startup Procedures
        2. 9.5.3.2 Shutdown Procedures
        3. 9.5.3.3 Protection and Monitoring
          1. 9.5.3.3.1 Overcurrent Limit (Cycle-By-Cycle)
          2. 9.5.3.3.2 Overcurrent Shutdown (OCSD)
          3. 9.5.3.3.3 DC Detect
    6. 9.6 Register Maps
      1. 9.6.1 CONTROL PORT Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Inductor Selections
      2. 10.1.2 Bootstrap Capacitors
      3. 10.1.3 Power Supply Decoupling
      4. 10.1.4 Output EMI Filtering
    2. 10.2 Typical Applications
      1. 10.2.1 2.0 (Stereo BTL) System
      2. 10.2.2 Design Requirements
      3. 10.2.3 Detailed Design procedures
        1. 10.2.3.1 Step One: Hardware Integration
        2. 10.2.3.2 Step Two: Hardware Integration
        3. 10.2.3.3 Step Three: Software Integration
      4. 10.2.4 Application Curves
      5. 10.2.5 MONO (PBTL) Systems
      6. 10.2.6 Advanced 2.1 System (Two TAS5825M Devices)
      7. 10.2.7 Application Curves
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 DVDD Supply
      2. 10.3.2 PVDD Supply
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
        1. 10.4.1.1 General Guidelines for Audio Amplifiers
        2. 10.4.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
        3. 10.4.1.3 Optimizing Thermal Performance
          1. 10.4.1.3.1 Device, Copper, and Component Layout
          2. 10.4.1.3.2 Stencil Pattern
            1. 10.4.1.3.2.1 PCB footprint and Via Arrangement
            2. 10.4.1.3.2.2 Solder Stencil
      2. 10.4.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Development Support
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

Figure 6-1 RHB Package32-Pin VQFN
Table 6-1 Pin Functions Table
PIN TYPE(1) DESCRIPTION
NAME NO.
DGND 5 P Digital ground
DVDD 6 P 3.3-V or 1.8-V digital power supply
VR_DIG 7 P Internally regulated 1.5-V digital supply voltage. This pin must not be used to drive external devices
ADR 8 AI A table of resistor value (Pull down to GND) decides device I2C address. See Table 9-5.
GPIO0 9 DI/O General-purpose input/output, function of this pin can be programmed by register (Register Address 0x60h and 0x61h). Can be configured to be CMOS output or Open drain output (WARNZ or FAULTZ)
GPIO1 10 DI/O General-purpose input/output, function of this pin can be programmed by register (Register Address 0x60h and 0x62h). Can be configured to be CMOS output or Open drain output (WARNZ or FAULTZ)
GPIO2 11 DI/O General-purpose input/output, function of this pin can be programmed by register (Register Address 0x60h and 0x63h). Can be configured to be CMOS output or Open drain output (WARNZ or FAULTZ)
LRCLK 12 DI Word select clock for the digital signal that is active on the serial port's input data line. In I2S, LJ and RJ, this corresponds to the left channel and right channel boundary. In TDM mode, this corresponds to the frame sync boundary.
SCLK(2) 13 DI Bit clock for the digital signal that is active on the input data line of the serial data port. Sometimes, this pin also be written as "bit clock (BCLK)"
SDIN 14 DI Data line to the serial data port
SDA 15 DI/O I2C serial control data interface input/output
SCL 16 DI I2C serial control clock input
PDN 17 DI Power down, active-low. PDN place the amplifier in Shutdown, turn off all internal regulators.
GVDD 18 P Gate drive internal regulator output. This pin must not be used to drive external devices
AVDD 19 P Internally regulated 5-V analog supply voltage. This pin must not be used to drive external devices
AGND 20 P Analog ground
PVDD 3 P PVDD voltage input
4 P
21 P
22 P
PGND 25 P Ground reference for power device circuitry. Connect this pin to system ground.
26 P
31 P
32 P
OUT_B+ 23 O Positive pin for differential speaker amplifier output B
BST_B+ 24 P Connection point for the OUT_B+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_B+
OUT_B- 27 O Negative pin for differential speaker amplifier output B
BST_B- 28 P Connection point for the OUT_B- bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_B-
BST_A- 29 P Connection point for the OUT_A- bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_A-
OUT_A- 30 O Negative pin for differential speaker amplifier output A
BST_A+ 1 P Connection point for the OUT_A+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_A+
OUT_A+ 2 O Positive pin for differential speaker amplifier output A
PowerPAD™ P Connect to the system Ground
(1) AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional (input and output), P = Power, G = Ground (0 V)
(2) Typically written "bit clock (BCLK)" in some audio codecs.