SCPS282B December   2022  – November 2023 TCA39416

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Voltage Waveforms
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Architecture
      2. 7.3.2 Enable and Disable
      3. 7.3.3 Pull up resistors on I/O Lines
      4. 7.3.4 Input Driver Requirements
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • 2-bit dual supply bidirectional translator for I3C, I2C, SMBus, SPI applications
  • Provides bidirectional voltage translation with no direction pin
  • High-impedance output Ax and Bx pins when
    OE = 0 V or VCC = 0 V
  • Internal 10-kΩ pull-up resistor on Ax and Bx pins
  • 0.72 V to 1.98 V on both A and B ports;
    VCCA ≤ VCCB
  • Compatible with MIPI I3C supporting speeds up to 12.5 MHz
  • Compatible with JEDEC I3C module sideband bus specification (JESD403)
  • VCC Isolation feature: If either VCC input is at GND, both A and B ports are in the high-impedance state
  • No power-supply sequencing required: either VCCA or VCCB can be ramped first
  • Low Ioff of 2.5 µA when either VCCA or VCCB = 0 V
  • OE input can be tied directly to VCCA or controlled by GPIO
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD Protection exceeds JESD 22
    • 4000-V Human-body model (A114-B)
    • 1500-V Charged-device model (C101)