SCPS273C may   2019  – june 2023 TCA9548A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Reset Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 RESET Input
      2. 8.4.2 Power-On Reset
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
      2. 8.5.2 Device Address
      3. 8.5.3 Bus Transactions
        1. 8.5.3.1 Writes
        2. 8.5.3.2 Reads
      4. 8.5.4 Control Register
      5. 8.5.5 RESET Input
      6. 8.5.6 Power-On Reset
  10.   Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  11.   Power Supply Recommendations
    1. 9.1 Power-On Reset Requirements
  12. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  13. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  14.   Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.1 Power-On Reset Requirements

In the event of a glitch or data corruption, TCA9548A-Q1 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.

A power-on reset is shown in Figure 9-1.

GUID-CFB5FD73-C7C0-4C7A-A125-55BEE23002A3-low.gif
VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC
Figure 9-1 Power-On Reset Waveform

Table 9-1 specifies the performance of the power-on reset feature for TCA9548A-Q1 for both types of power-on reset.

Table 9-1 Recommended Supply Sequencing and Ramp Rates(1)
PARAMETERMINMAXUNIT
VCC_FTFall timeSee Figure 9-11100ms
VCC_RTRise timeSee Figure 9-10.1100ms
VCC_TRRTime to re-ramp (when VCC drops below VPORF(min) – 50 mV or when VCC drops to GND)See Figure 9-140μs
VCC_GHLevel that VCC can glitch down to, but not cause a functional disruption when VCC_GW = 1 μsSee Figure 9-21.2V
VCC_GWGlitch width that does not cause a functional disruption when VCC_GH = 0.5 × VCCSee Figure 9-210μs
(1) All supply sequencing and ramp rate values are measured at TA = 25°C

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 9-2 and Table 9-1 provide more information on how to measure these specifications.

GUID-4E3E768B-F8D9-4FCE-9FEC-F1DAB2F4F92A-low.gifFigure 9-2 Glitch Width and Glitch Height

VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 9-3 and Table 9-1 provide more details on this specification.

GUID-419E9CA3-9DC4-44D8-9173-F6C501273074-low.gifFigure 9-3 VPOR Example