SLLSFW8 June   2024 TCAN1472-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configurations and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 ESD Ratings, IEC Transients
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Characteristics
    6. 5.6 Supply Characteristics
    7. 5.7 Dissipation Ratings
    8. 5.8 Electrical Characteristics
    9. 5.9 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Signal Improvement
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pin Description
        1. 7.3.1.1 TXD
        2. 7.3.1.2 GND
        3. 7.3.1.3 VCC
        4. 7.3.1.4 RXD
        5. 7.3.1.5 VIO (TCAN1472V-Q1 only)
        6. 7.3.1.6 CANH and CANL
        7. 7.3.1.7 STB (Standby)
      2. 7.3.2 CAN Bus States
      3. 7.3.3 TXD Dominant Timeout (DTO)
      4. 7.3.4 CAN Bus Short-circuit Current Limiting
      5. 7.3.5 Thermal Shutdown (TSD)
      6. 7.3.6 Undervoltage Lockout
      7. 7.3.7 Unpowered Device
      8. 7.3.8 Floating pins
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes
      2. 7.4.2 Normal Mode
      3. 7.4.3 Standby Mode
        1. 7.4.3.1 Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode
      4. 7.4.4 Driver and Receiver Function
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 CAN Termination
      2. 8.2.2 Detailed Design Procedures
        1. 8.2.2.1 Bus Loading, Length and Number of Nodes
    3. 8.3 System Examples
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DDF|8
  • DRB|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.8 Electrical Characteristics

parameters valid over recommended operating conditions with -40℃ ≤ TJ ≤ 150℃ (Typical values are at VCC = 5 V, VIO = 3.3 V, Device ambient maintained at 27℃ ) unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Driver Electrical Characteristics
VCANH(D) Dominant output voltage normal mode  CANH VCC = 4.5 V to 5.5 V, TXD = 0 V, STB = 0 V
50 Ω ≤ RL ≤ 65 Ω, CL = open,
See Figure 6-2 and Figure 7-5		 2.75 3.5 4.5 V
VCANL(D) CANL 0.5 1.5 2.25 V
VCANH(D) Dominant output voltage normal mode CANH VCC = 4.75 V to 5.25 V, TXD = 0 V, STB = 0 V
45 Ω ≤ RL ≤ 65 Ω, CL = open,
See Figure 6-2 and Figure 7-5		 3 3.5 4.26 V
VCANL(D) CANL 0.75 1.5 2.01 V
VCANH(R), VCANL(R) Recessive output voltage normal mode CANH and CANL VCC = 4.5 V to 5.5 V, TXD = VIO, STB = 0 V
RL = open (no load), CL = open,
See Figure 6-2 and Figure 7-5		 2 2.5 3 V
VCANH(R), VCANL(R) Recessive output voltage normal mode CANH and CANL VCC = 4.75 V to 5.25 V, TXD = VIO, STB = 0 V
45 Ω ≤ RL ≤ 65 Ω , CL = 4.7 nF See Figure 6-2 and Figure 7-5		 2.256 2.756 V
VSYM Driver symmetry
(VO(CANH) + VO(CANL))/(VCANH(R) + VCANL(R))		 TXD = 250 kHz, 1 MHz, 2.5 MHz, STB = 0 V
45 Ω ≤ RL ≤ 65 Ω, CSPLIT = 4.7 nF, CL = open,
See Figure 6-2 and Figure 7-5		 0.95 1.05 V/V
VDIFF(D) Differential output voltage normal mode
Dominant		 CANH - CANL TXD = 0 V, STB = 0 V
45 Ω ≤ RL ≤ 65 Ω, CL = open,
See Figure 6-2 and Figure 7-5		 1.5 3 V
TXD = 0 V, STB = 0 V
45 Ω ≤ RL ≤ 70 Ω, CL = open,
See Figure 6-2 and Figure 7-5		 1.5 3.3 V
TXD = 0 V, STB = 0 V
RL = 2240 Ω, CL = open,
See Figure 6-2 and Figure 7-5		 1.5 5 V
VDIFF(R) Differential output voltage normal mode
Recessive		 CANH - CANL TXD = VIO, STB = 0 V
45 Ω ≤ RL ≤ 65 Ω, CSPLIT = 4.7 nF, CL = open,
See Figure 6-2 and Figure 7-5		 –50 50 mV
TXD = VIO, STB = 0 V
RL = open, CL = open,
See Figure 6-2 and Figure 7-5		 –50 50 mV
VCANH(INACT) Bus output voltage standby mode CANH TXD = STB = VIO
RL = open , CL = open,
See Figure 6-2 and Figure 7-5		 -0.1 0.1 V
VCANL(INACT) CANL -0.1 0.1 V
VDIFF(INACT) CANH - CANL -0.2 0.2 V
RDIFF(DOM) Differential input resistance in dominant phase TXD= 0 V, STB = 0 V, See Figure 7-2  40 Ω
RSE_SIC_ACT_REC Single ended resistance CANH/CANL in active recessive phase 2 V ≤ VCANH/L ≤ VCC - 2 V
 37.5 50 66.5 Ω
RDIFF_SIC_ACT_REC Differential input resistance in active recessive drive phase 2 V ≤ VCANH/L ≤ VCC - 2 V
 75 100 133 Ω
ICANH(OS) Short-circuit bus output current, TXD is dominant or recessive or toggling, normal mode V(CANH) = -15 V to 40 V, CANL = open, TXD = 0 V or VIO or 250 kHz, 2.5 MHz square wave, 
See Figure 6-7 and Figure 7-5		 –115 115 mA
 ICANL(OS) V(CAN_L) = -15 V to 40 V, CANH = open, TXD = 0 V or VIO or 250 kHz, 2.5 MHz square wave,
See Figure 6-7 and Figure 7-5		 –115 115 mA
Receiver Electrical Characteristics
VIT Input threshold voltage normal mode  -12 V ≤ VCM ≤ 12 V, STB= 0 V,
See Figure 6-3 and Figure 7-6		 500 900 mV
VIT(STB) Input threshold standby mode  -12 V ≤ VCM ≤ 12 V, STB= VIO ,
See Figure 6-3 and Figure 7-6		 400 1150 mV
VDIFF_RX(D) Normal mode dominant state differential input voltage range  -12 V ≤ VCM ≤ 12 V, STB= 0 V,
See Figure 6-3 and Figure 7-6		 0.9 9 V
VDIFF_RX(R) Normal mode recessive state differential input voltage range -12 V ≤ VCM ≤ 12 V , STB= 0 V,
See Figure 6-3 and Figure 7-6		 -4 0.5 V
VDIFF_RX(D_INACT) Standby mode dominant state differential input voltage range STB = VIO, -12 V ≤ VCM ≤ 12 V,
See Figure 6-3 and Figure 7-6		 1.15 9 V
VDIFF_RX(R_INACT) Standby mode recessive state differential input voltage range STB = VIO, -12 V ≤ VCM ≤ 12 V,
See Figure 6-3 and Figure 7-6		 -4 0.4 V
VHYS Hysteresis voltage for input threshold normal mode  -12 V ≤ VCM ≤ 12 V, STB= 0 V,
See Figure 6-3 and Figure 7-6		 100 mV
VCM Common mode range normal and standby modes See Figure 6-3 and Figure 7-6 –12 12 V
ILKG(OFF) Unpowered bus input leakage current CANH = CANL = 5 V,  VCC = VIO = GND 5 µA
CI Input capacitance to ground (CANH or CANL) TXD = VIO   30 pF
CID Differential input capacitance across bus terminals 15 pF
RDIFF_PAS_REC Differential input resistance in passive recessive phase TXD = VIO, STB = 0 V -12 V ≤ VCM ≤ 12 V, Delta V/Delta I 40 90 kΩ
RSE_PAS_REC Single ended input resistance in passive recessive phase
(CANH or CANL)		 20 45 kΩ
mR Input resistance matching
[1 – (RIN(CANH) / RIN(CANL))] × 100 %		 V(CAN_H) = V(CAN_L) = 5 V –1 1 %
TXD Terminal (CAN Transmit Data Input)
VIH High-level input voltage Devices without VIO 0.7 VCC V
VIH High-level input voltage Devices with VIO 0.7 VIO V
VIL Low-level input voltage Devices without VIO 0.3 VCC V
VIL Low-level input voltage Devices with VIO 0.3 VIO V
IIH High-level input leakage current TXD = VCC = VIO = 5.5 V –2.5 0 1 µA
IIL Low-level input leakage current TXD = 0 V, VCC = VIO = 5.5 V –200 -100 –20 µA
ILKG_TXD(OFF) Unpowered leakage current TXD = 5.5 V, VCC = VIO = 0 V –1 0 1 µA
CI_TXD Input capacitance VIN = 0.4×sin(2×π×2×106×t)+2.5 V 6 pF
RXD Terminal (CAN Receive Data Output)
VOH High-level output voltage Devices without VIO
IO = –1.5 mA,
See Figure 6-3		 0.8 VCC V
VOH High-level output voltage IO = –1.5 mA, Devices with VIO
See Figure 6-3		 0.8 VIO   V
VOL Low-level output voltage Devices without VIO
IO = 1.5 mA,
See Figure 6-3		 0.2 VCC V
VOL Low-level output voltage Devices with VIO
IO = 1.5 mA, Devices with VIO
See Figure 6-3		   0.2 VIO V
ILKG_RXD(OFF) Unpowered leakage current RXD = 5.5 V, VCC = VIO = 0 V –1 0 1 µA
 STB Terminal (Standby Mode Input)
VIH High-level input voltage Devices without VIO 0.7 VCC V
VIH High-level input voltage Devices with VIO 0.7 VIO V
VIL Low-level input voltage Devices without VIO 0.3 VCC V
VIL Low-level input voltage Devices with VIO 0.3 VIO V
IIH High-level input leakage current  VCC = VIO = STB = 5.5 V –2 2 µA
IIL Low-level input leakage current  VCC = VIO = 5.5 V, STB = 0 V –20 –2 µA
ILKG_STB(OFF) Unpowered leakage current STB = 5.5V, VCC= VIO = 0 V –1 0 1 µA