SLLSEQ7E December   2015  – December 2019 TCAN330 , TCAN330G , TCAN332 , TCAN332G , TCAN334 , TCAN334G , TCAN337 , TCAN337G

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Block Diagram
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Options
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Switching Characteristics
    7. 8.7 Typical Characteristics
    8. 8.8 Typical Characteristics, TCAN330 Receiver
    9. 8.9 Typical Characteristics, TCAN330 Driver
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 TXD Dominant Timeout (TXD DTO)
      2. 10.3.2 RXD Dominant Timeout (RXD DTO)
      3. 10.3.3 Thermal Shutdown
      4. 10.3.4 Undervoltage Lockout and Unpowered Device
      5. 10.3.5 Fault Pin (TCAN337)
      6. 10.3.6 Floating Pins
      7. 10.3.7 CAN Bus Short Circuit Current Limiting
      8. 10.3.8 ESD Protection
      9. 10.3.9 Digital Inputs and Outputs
    4. 10.4 Device Functional Modes
      1. 10.4.1 CAN Bus States
      2. 10.4.2 Normal Mode
      3. 10.4.3 Silent Mode
      4. 10.4.4 Standby Mode with Wake
      5. 10.4.5 Bus Wake via RXD Request (BWRR) in Standby Mode
      6. 10.4.6 Shutdown Mode
      7. 10.4.7 Driver and Receiver Function Tables
  11. 11Application and Implementation
    1. 11.1 Application Information
      1. 11.1.1 Bus Loading, Length and Number of Nodes
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
        1. 11.2.1.1 CAN Termination
      2. 11.2.2 Detailed Design Procedure
      3. 11.2.3 Application Curves
    3. 11.3 System Examples
      1. 11.3.1 ISO11898 Compliance of TCAN33x Family of 3.3-V CAN Transceivers Introduction
      2. 11.3.2 Differential Signal
      3. 11.3.3 Common-Mode Signal and EMC Performance
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Related Links
    2. 14.2 Support Resources
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5 Electrical Characteristics

over operating free-air temperature range, TJ = –40°C to 150°C. All typical values are at 25°C and supply voltages of VCC = 3.3 V, RL = 60 Ω, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply
ICC Supply current Normal Mode Dominant See Figure 18. TXD = 0 V, RL = 60 Ω, CL = open, S, STB and SHDN = 0 V. Typical Bus Load. 55 mA
See Figure 18. TXD = 0 V, RL = 50 Ω, CL = open, S, STB and SHDN = 0 V. High Bus Load. 60
Dominant with bus fault See Figure 18. TXD = 0 V, S, STB and SHDN = 0 V, CANH = -12 V, RL = open, CL = open 180
Recessive See Figure 18. TXD = VCC, RL = 50 Ω, CL = open, S, STB and SHDN = 0 V 3.5
Supply Current: Silent Mode See Figure 18. TXD = VCC, RL = 50 Ω, CL = open, S = VCC 2.5
Supply Current: Standby Mode TA < 85°C, STB at VCC, RXD floating, TXD at VCC 15 µA
STB at VCC, RXD floating, TXD at VCC 20
Supply Current: Shutdown Mode TA < 85°C, SHDN at VCC, RXD floating, TXD at VCC 1
SHDN = VCC, RXD floating, TXD at VCC 2.5
UV(VCC) Rising under voltage detection on VCC for protected mode 2.2 2.6 V
Falling under voltage detection on VCC for protected mode 1.65 2 2.5
VHYS(UVVCC) Hysteresis voltage on UV(VCC) 200 mV
Driver
VO(D) Bus output voltage (dominant) CANH See Figure 31 and Figure 19, TXD = 0 V, S, STB and SHDN = 0 V, RL = 60 Ω, CL = open 2.45 VCC V
CANL 0.5 1.25
VO(R) Bus output voltage (recessive) See Figure 31 and Figure 19, TXD = VCC, STB, SHDN = 0 V, S = 0 V or VCC(1), RL = open (no load) 1.85 V
VOD(D) Differential output voltage (dominant) See Figure 31 and Figure 19, TXD = 0 V, S, STB and SHDN = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open 1.6 3 V
See Figure 31 and Figure 19, TXD = 0 V, S, STB and SHDN = 0 V, 45 Ω ≤ RL < 50 Ω, CL = open 1.5 3
VOD(R) Differential output voltage (recessive) See Figure 31 and Figure 19, TXD = VCC, S, STB and SHDN = 0 V, RL = 60 Ω, CL = open –120 12 mV
TA < 85°C, See Figure 31 and Figure 19, TXD = VCC, S, STB and SHDN = 0 V, RL = open (no load), CL = open –50 50
See Figure 31 and Figure 19, TXD = VCC, S, STB and SHDN = 0 V, RL = open (no load), CL = open –50 100
V(SYM) Output symmetry (dominant and recessive)
(CANHREC + CANLREC – CANHDOM – CANLDOM)		 See Figure 31 and Figure 19, S, STB and SHDN = 0 V, RL = 60 Ω, CL = open –400 400 mV
IOS(DOM) Short-circuit steady-state output current, Dominant See Figure 26, V(CANH) = –12 V, CANL = open, TXD = 0 V –200 mA
See Figure 26, V(CANL) = 12 V, CANH = open, TXD = 0 V 200
IOS(REC) Short-circuit steady-state output current, Recessive See Figure 26, –12 V ≤ VBUS ≤ 12 V, VBUS = CANH = CANL, TXD = VCC –5 5 mA
Receiver
VIT Input threshold voltage, normal modes and selective wake modes See Figure 20 and Table 7 500 900 mV
VHYS Hysteresis voltage for input threshold, normal modes and selective wake modes 120
VCM Common Mode Range: normal and silent modes –12 12 V
VIT(STB) Input Threshold, standby mode –2 V < VCM < 7 V
See Figure 20 and Table 7 		400 1150 mV
–12 V < VCM < 12 V
See Figure 20 and Table 7 		400 1350 mV
IIOFF(LKG) Power-off (unpowered) bus input leakage current TA < 85°C, CANH = CANL = 3.3 V, VCC to GND via 0-Ω and 47-kΩ resistor 6 µA
CANH = CANL = 3.3 V, VCC to GND via 0-Ω and 47-kΩ resistor 12
CI Input capacitance to ground (CANH or CANL) 20 pF
CID Differential input capacitance 10
RID Differential input resistance TXD = VCC, Normal Mode 30 80 kΩ
RIN Input resistance (CANH or CANL) TXD = VCC, Normal mode 15 40
RIN(M) Input resistance matching: [1 – (RIN(CANH) / RIN(CANL))] × 100 % V(CANH) = V(CANL) –3% 3%
TXD Terminal (CAN Transmit Data Input)
VIH HIGH level input voltage 2 V
VIL LOW level input voltage 0.8 V
IIH HIGH level input leakage current TXD = VCC = 3.6 V –2.5 0 3 µA
IIL LOW level input leakage current TXD = 0 V, VCC = 3.6 V –4 0 0 µA
ILKG(OFF) Unpowered leakage current TXD = 3.6 V, VCC = 0 V –2 0 2.5 µA
I(CAP) Input Capacitance 2.5 pF
RXD Terminal (CAN Receive Data Output)
VOH HIGH level output voltage See Figure 20, IO = –2 mA 0.8 x VCC V
VOL LOW level output voltage See Figure 20, IO = 2 mA 0.2 0.4 V
ILKG(OFF) Unpowered leakage current RXD = 3.6 V, VCC = 0 V –1 0 1 µA
STB/S/SHDN Terminals
VIH HIGH level input voltage 2 V
VIL LOW level input voltage 0.8 V
IIH HIGH level input leakage current STB, S, SHDN = VCC = 3.6 V –3 0 10 µA
IIL LOW level input leakage current STB, S, SHDN = 0 V, VCC = 3.6 V –4 0 1 µA
ILKG(OFF) Unpowered leakage current STB, S, SHDN = 3.6 V, VCC = 0 V –3 0 5 µA
FAULT Pin (Fault Output), TCAN337 only
ICH Output current high level FAULT = VCC, See Figure 28 –10 µA
ICL Output current low level FAULT = 0.4 V, See Figure 28 4 12 mA
(1) The bus output voltage (recessive) will be the same if the device is in normal mode with S terminal LOW or if the device is in silent mode with the S terminal is HIGH.