SPRSP62B December 2022 – December 2024 TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Table 6-29, Section 6.10.5.2.2.1, Section 6.10.5.2.2.2, and Section 6.10.5.2.2.3 present timing conditions, requirements, and switching characteristics for CPSW2G RMII.
PARAMETER | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
INPUT CONDITIONS | |||||
SRI | Input signal slew rate | VDD(1) = 1.8 V | 0.108 | 0.54 | V/ns |
VDD(1) = 3.3 V | 0.4 | 1.2 | V/ns | ||
OUTPUT CONDITIONS | |||||
CL | Output load capacitance | 3 | 25 | pF |