SLDS120 Data sheet

SLDS120H March 2000 – March 2022 TFP401 , TFP401A

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

PZP|100
- MPQF053D

Thermal pad, mechanical data (Package|Pins)

PZP|100
- PPTD033I

Orderable Information

7.7 AC Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_ID(2)	Differential input sensitivity⁽¹⁾		150		1560	mV_p-p
t_ps	Analog input intra-pair (+ to –) differential skew⁽⁸⁾				0.4	t_bit⁽²⁾
t_ccs	Analog input inter-pair or channel-to-channel skew ⁽⁸⁾				1	t_pix⁽³⁾
t_ijit	Worst-case differential input clock jitter tolerance⁽⁸⁾⁽⁴⁾		50			ps
t_f1	Fall time of data and control signals⁽⁵⁾⁽⁶⁾	ST = low, C_L = 5 pF			2.4	ns
t_f1	Fall time of data and control signals⁽⁵⁾⁽⁶⁾	ST = high, C_L = 10 pF			1.9	ns
t_r1	Rise time of data and control signals⁽⁵⁾⁽⁶⁾	ST = low, C_L = 5 pF			2.4	ns
t_r1	Rise time of data and control signals⁽⁵⁾⁽⁶⁾	ST = high, C_L = 10 pF			1.9	ns
t_r2	Rise time of ODCK clock⁽⁵⁾	ST = low, C_L = 5 pF			2.4	ns
t_r2	Rise time of ODCK clock⁽⁵⁾	ST = high, C_L = 10 pF			1.9	ns
t_f2	Fall time of ODCK clock⁽⁵⁾	ST = low, C_L = 5 pF			2.4	ns
t_f2	Fall time of ODCK clock⁽⁵⁾	ST = high, C_L = 10 pF			1.9	ns
t_su1	Setup time, data and control signal to falling edge of ODCK	1 pixel/clock, PIXS = low, OCK_INV = low	1.8			ns
		2 pixel/clock, PIXS = high, STAG = high, OCK_INV = low	3.8
		2 pixel and STAG, PIXS = high, STAG = low, OCK_INV = low	0.7
t_h1	Hold time, data and control signal to falling edge of ODCK	1 pixel/clock, PIXS = low, OCK_INV = low	0.6			ns
		2 pixel and STAG, PIXS = high, STAG = low, OCK_INV = low	2.5
		2 pixel/clock, PIXS = high, STAG = high, OCK_INV = low	2.9
t_su2	Setup time, data and control signal to rising edge of ODCK	1 pixel/clock, PIXS = low, OCK_INV = high	2.1			ns
		2 pixel/clock, PIXS = high, STAG = high, OCK_INV = high	4
		2 pixel and STAG, PIXS = high, STAG = low, OCK_INV = high	1.5
t_h2	Hold time, data and control signal to rising edge of ODCK	1 pixel/clock, PIXS = low, OCK_INV = high	0.5			ns
		2 pixel and STAG, PIXS = high, STAG = low, OCK_INV = high	2.4
		2 pixel/clock, PIXS = high, STAG = high, OCK_INV = high	2.1
f_ODCK	ODCK frequency	PIX = low (1-PIX/CLK)	25		165	MHz
f_ODCK	ODCK frequency	PIX = high (2-PIX/CLK)	12.5		82.5	MHz
	ODCK duty-cycle		40%	50%	60%
t_pd(PDL)	Propagation delay time from PD low to Hi-Z outputs				9	ns
t_pd(PDOL)	Propagation delay time from PDO low to Hi-Z outputs				9	ns
t_t(HSC)	Transition time between DE transition to SCDT low⁽⁷⁾			1e6		t_pix
t_t(FSC)	Transition time between DE transition to SCDT high⁽⁷⁾			1600		t_pix
t_d(st)	Delay time, ODCK latching edge to QE[23:0] data output	STAG = low, PIXS = high		0.25		t_pix
t_{WL(PDL_MIN)}	Minimum time PD is asserted low		9			ns
t_DEL	Minimum DE low		128			Tpixel

(1) Specified as ac parameter to include sensitivity to overshoot, undershoot and reflection.

(2) t_bit is 1/10 the pixel time, t_pix.

(3) t_pix is the pixel time defined as the period of the RxC input clock. The period of ODCK is equal to t_pix in 1-pixel/clock mode or 2t_pix when in 2-pixel/clock mode.

(4) Measured differentially at 50% crossing using ODCK output clock as trigger.

(5) Rise and fall times measured as time between 20% and 80% of signal amplitude.

(6) Data and control signals are QE[23:0], QO[23:0], DE, HSYNC, VSYNC. and CTL[3:1].

(7) Link active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity.

(8) By characterization.