SLDS120H March   2000  – March 2022 TFP401 , TFP401A

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings (1)
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Digital I/O Electrical Characteristics
    6. 7.6 DC Electrical Characteristics
    7. 7.7 AC Electrical Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 TMDS Pixel Data and Control Signal Encoding
      2. 9.3.2 TFP401/401A Clocking and Data Synchronization
      3. 9.3.3 TFP401/401A TMDS Input Levels and Input Impedance Matching
      4. 9.3.4 TFP401A Incorporates HSYNC Jitter Immunity
    4. 9.4 Device Functional Modes
      1. 9.4.1 TFP401/401A Modes of Operation
      2. 9.4.2 TFP401/401A Output Driver Configurations
        1. 9.4.2.1 Output Driver Power Down
        2. 9.4.2.2 Drive Strength
        3. 9.4.2.3 Time-Staggered Pixel Output
        4. 9.4.2.4 Power Management
        5. 9.4.2.5 Sync Detect
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Data and Control Signals
        2. 10.2.2.2 Configuration Options
        3. 10.2.2.3 Power Supplies Decoupling
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Layer Stack
      2. 12.1.2 Routing High-Speed Differential Signal Traces (RxC–, RxC+, Rx0–, Rx0+, Rx1–, Rx1+, Rx2–, Rx2+)
      3. 12.1.3 DVI Connector
    2. 12.2 Layout Example
    3. 12.3 TI PowerPAD 100-TQFP Package
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Support Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3 Recommended Operating Conditions

MINNOMMAXUNIT
VDD (DVDD, AVDD, PVDD, OVDD)Supply voltage33.33.6V
tpix (1)Pixel time6.0640ns
RtSingle-ended analog-input termination resistance455055Ω
TAOperating free-air temperature02570°C
(1) tpix is the pixel time defined as the period of the RxC clock input. The period of the output clock, ODCK is equal to tpix when in 1-pixel/clock mode and 2tpix when in 2-pixel/clock mode.