SBOS932C January   2020  – March 2021 THP210

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Characterization Configuration
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Super-Beta Input Bipolar Transistors
      2. 8.3.2 Power Down
      3. 8.3.3 Flexible Gain Setting
      4. 8.3.4 Amplifier Overload Power Limit
      5. 8.3.5 Unity Gain Stability
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 I/O Headroom Considerations
      2. 9.1.2 DC Precision Analysis
        1. 9.1.2.1 DC Error Voltage at Room Temperature
        2. 9.1.2.2 DC Error Voltage Over Temperature
      3. 9.1.3 Noise Analysis
      4. 9.1.4 Mismatch of External Feedback Network
      5. 9.1.5 Operating the Power-Down Feature
      6. 9.1.6 Driving Capacitive Loads
      7. 9.1.7 Driving Differential ADCs
        1. 9.1.7.1 RC Filter Selection (Charge Kickback Filter)
        2. 9.1.7.2 Settling Time Driving the ADC Sample-and-Hold Operating Behavior
        3. 9.1.7.3 THD Performance
    2. 9.2 Typical Applications
      1. 9.2.1 MFB Filter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 ADS891x With Single-Ended RC Filter Stage
        1. 9.2.2.1 Design Requirements
          1. 9.2.2.1.1 Measurement Results
      3. 9.2.3 Attenuation Configuration Drives the ADS8912B
        1. 9.2.3.1 Design Requirements
          1. 9.2.3.1.1 Measurement Results
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Layout Recommendations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.1.2.1 DC Error Voltage at Room Temperature

Good dc linearity allows the designer to minimize the total dc output error of the system. In particular, this error divides into two contributions: the initial error at the normal operating condition of 25°C, and the drift error over temperature. The main sources of these errors typically arise from:

  • Voltage error due to the input offset voltage (VIO)
  • Voltage error due to noninverting and inverting bias current (IB–, IB+)
  • The common-mode rejection ratio (CMRR) of the FDA
  • Voltage error due to mismatch between input and output common-mode voltages (VVOCM – VICM)

One major source of error comes from the effect of mismatched resistor values and the ratios on the two sides of the FDA. For this analysis, this error term is neglected. The effects are described separately in Section 9.1.4.

The THP210 super-beta input device features extremely-low input bias current, trimmed low input offset voltage, and the lowest offset drift over the full temperature operating range. These features allow the device to produce a negligible initial error band at 25°C, but also exceptional robust behavior over temperature. The red curve in Figure 9-1 showcases a simulation of the total dc error voltage at 25°C versus different gain configurations based on the application configuration shown in Figure 9-2.

GUID-933B4881-D089-4E13-9D5B-2EB12B7D45EC-low.gif Figure 9-1 TINA-TI™ Software Simulation of DC Error Voltage at Different Gain Settings (Variable R2)
GUID-63A1F774-545C-423C-AF82-4360040C0D2A-low.gif Figure 9-2 FDA DC Error Model

One use case at a differential input voltage of VID = 200 mV and a gain of 5 V/V (that corresponds to R2 = 5 kΩ) reveals that the initial dc error of the THP210 is 4.5 µV. A comparable FDA2 with VIO = 200 µV,
IB = 650 nA, and IIO = 30 nA results in a 2.22-mV dc error voltage that results in a factor of approximately 500 higher dc error.

In addition, Figure 9-3 shows that the absolute dc accuracy of the THP210 nearly adds an error voltage on the system. The dominant factors for the initial error band are mainly due to the feedback resistor mismatch that is not considered in the simulation plot.