A wideband CFA provides a flexible output driver with several unique features. The OPS can be left unused if the specific application only uses the D2S alone, or a combination of the D2S with an off-chip power driver. If left unused, simply tie DISABLE (pin 10) and PATHSEL (pin 4) to the positive supply. This logic configuration turns the OPS off and opens up the external and internal OPS noninverting input paths. An internal fixed 18.5 kΩ resistor holds the external input pin at the logic reference voltage on GND (pin 7). Additionally, the OPS output is connected to the inverting input through another internal 18.5 kΩ resistor when no external resistors are installed on VIN+, VOUT, or VIN– (pins 9, 11, or 12, repectively). Disabling the OPS saves approximately 11 mA of supply current from the nominal total 35 mA, with all stages operating on ±6 V supplies.

The noninverting input to the OPS provides two possible paths controlled by the PATHSEL logic control. With the logic reference (pin 7) at ground, floating PATHSEL or controlling it to a voltage < 0.7 V connects the input path directly to the internal D2S output. Tying PATHSEL to the positive supply, or controlling it to a logic level > 1.3 V, connects the input path to the external input at VIN+. The intent for this switched input is to allow an external filter to be inserted between the D2S output and OPS inputs when needed, and bypass the filter when not. Alternatively, this switched input also allows a completely different signal path to be inserted at the OPS input, independent of that available at the internal D2S output.

In situations where the D2S output at VO1 (pin 6) is switched into another off-chip power driver, the OPS can be disabled using DISABLE. With the logic reference (pin 7) at ground, floating DISABLE, or controlling it to a voltage < 0.7 V, enables the OPS. Tying DISABLE to the positive supply, or controlling it to a logic level > 1.3 V, disables the OPS.

Operation of the wideband, current-feedback OPS requires an external feedback resistor and a gain element. After configuring, the OPS can amplify the D2S output through either the noninverting path, or be configured as an inverting amplifier stage using the external OPS input at VIN+ as a dc reference.

One of the first considerations when designing with the OPS is determining the external resistor values as a function of gain in order to hold the best ac performance. The loop gain (LG) of a CFA is set by the internal open-loop transimpedance gain from the inverting error current to the output, and the effective feedback impedance to the inverting input. The nominal internal open-loop transimpedance gain (Z_OL) magnitude and phase are shown in Figure 8-7.

The feedback transimpedance (Z_OPT) can be approximated as shown in Equation 11, where R_i is the open-loop, high-frequency impedance into the inverting node of the OPS. For a detailed derivation of Equation 11, see the Setting Resistor Values to Optimize Bandwidth section in the OPA695 datasheet (SBOS293).

As the signal gain is varied, hold Z_OPT approximately constant to hold the ac response constant over gain. Holding Z_OPT constant is a requirement to solve for R_F. An example of the THS3215 OPS R_F derivation is shown in Equation 12:

The calculations are complicated by the internal feedback resistor value of approximately 18.5 kΩ. After the external R_F is approximately set by the constant bandwidth consideration, the R_G must be set considering the other gain error terms. From the noninverting input of a CFA, the total gain to the output includes a loss through the input buffer stage (described by the CMRR) and the loop gain (LG) loss set by the typical dc open-loop transimpedance gain and the feedback transimpedance. Extract the buffer gain from the VIN+ input to the VIN– input from the CMRR using Equation 13. This gain loss only applies to the noninverting mode of operation and can be ignored in inverting mode operation.

The OPS has a typical CMRR of 53 dB (buffer gain, β = 0.9978) with a tested minimum of 47 dB (minimum buffer gain of 0.9955). The dc LG adds to the gain error. The LG is given by Equation 14, where the typical design gain of 2.5 V/V value is also shown (the 245 Ω shown for R_F is the external 249 Ω feedback resistor in parallel with the internal 18.5 kΩ feedback resistor).

The closed-loop output impedance with a heavy load also adds a minor gain loss that is neglected here. The total noninverting gain is then set by Equation 15 (remember to include the internal R_F in this analysis). The R_F’ shown here is the parallel combination of the internal and external feedback resistors.

Using nominal values for each term at the specified R_F = 249 Ω and R_G = 162 Ω gives the gain calculation in Equation 16, yielding a nominal gain very close to 2.5 V/V.

Testing the total gain spread with the internal variation in buffer gain, open-loop transimpedance gain, internal feedback resistor, and ±1% external resistor variation gives a worst-case gain spread of 2.5 V/V to 2.52 V/V. The gain error is primarily dominated by the external 1% resistors. For the tighter tolerance shown in Table 8-1, use 0.1% precision resistors.

At very low gains (< 1.5 V/V), parasitic effects at the inverting input due to stray inductance and capacitance render a flat frequency response impossible. Looking then at gains from 1.5 V/V and up, a table of nominally recommended R_F and R_G values is shown in Table 8-1. Do not operate the OPS in noninverting gains of less than 2.5 V/V for large output signals because the limited slew-rate of the CFA input buffer causes signal degradation. Table 8-1 accounts for the nominal gain losses described previously, and uses standardized resistor values to minimize the nominal gain-error to target gain. The calculation also restricts the solution to a minimum R_G = 20 Ω. The gain calculations include the nominal buffer gain loss, the loop-gain effect, and the nominal internal feedback resistor = 18.5 kΩ.

The measured bandwidths in Table 8-1 come from Figure 6-25 using the resistor values in the table and a 100 Ω load. Plotting the R_F value versus gain gives the curve of Figure 8-8. The curve shows some ripple due to the standard value resistors used to minimize the target dc gain error.

Using R_F values greater than the recommended values in Table 8-1 band-limits the response, whereas using less than the recommended R_F values peaks the response. Using the values shown in Table 8-1 results in a more constant SSBW (see Figure 6-25. Holding a more constant loop-gain over the external gain setting also acts to hold a more constant output impedance profile, as shown in Figure 8-9. The swept-frequency, closed-loop, output impedance is shown for gains of 2.5 V/V, 5 V/V, and 10 V/V using the R_F and R_G values of Table 8-1. The first two steps do a good job of delivering the same (and very low) output impedance over frequency, while the gain of 10 V/V shows the expected higher closed-loop output impedance due to the reduced loop-gain and bandwidth.

Reducing the R_F value with increasing gain also helps minimize output noise versus a fixed R_F design. See Figure 6-39 for the three noise terms for the OPS. The total output noise calculation is shown in Equation 17:

where

• R_S is the source impedance on the noninverting input. If the OPS is driven from the D2S directly using the internal path, R_S ≈ 0 Ω.
• NG = (1 + R_F / R_G) for the design point.
• The flat-band noise numbers for the OPS are:
  • E_ni = 2.7 nV/√ Hz
  • I_bn = 1.3 pA/√ Hz
  • I_bi = 18 pA/√ Hz

Using the values of R_F and R_G listed in Table 8-1, a swept gain output- and input-referred noise estimate is computed, as shown in Table 8-2. In this sweep, R_S = 0 Ω. The input-referred noise (E_ni) in Table 8-1 is at the noninverting input of the OPS. To refer the noise to the D2S differential inputs, divide the output noise by two if there is no interstage loss. Dividing the E_ni column by 2 V/V shows that the OPS noise contribution is negligible when referred to the D2S inputs, where the 6 nV/√ Hz differential input noise dominates. Operating with higher feedback resistors in the OPS quickly increases the output noise due to the inverting input current noise term. Although increasing R_F improves phase margin (for example, when driving a capacitive load), be careful to check the total output noise using Equation 17.

Operating the OPS as an inverting amplifier is also possible. When driving the OPS directly from the D2S to the R_G resistor, use the values shown in Table 8-1 for the noninverting mode in order to achieve optimal results. Note that the R_G resistor is the load for the D2S. Operating with the D2S driving an R_G < 80 Ω increases the harmonic distortion of the D2S. In that case, scaling up R_F and R_G in order to reduce the loading results in better system performance at the cost of a lower OPS bandwidth. In order to reduce layout parasitics, consider splitting the R_G resistor in two, with the first half close to VO1 and the second half close to VIN– (pin 12). Splitting R_G in this manner places the trace capacitance inside the two resistors, thus keeping both active nodes more stable.

Using the OPS to receive and amplify a signal in the inverting mode with a matched terminating impedance requires another resistor to ground (R_M) along with R_G. This R_M resistor is shown in Figure 8-10 for a 50 Ω matched input impedance design.

Table 8-3 gives the recommended external resistor values versus gain for the inverting gain mode with input matching configuration. Table 8-3 solves for the required R_F to simultaneously allow the gain, input impedance (50 Ω), and feedback transimpedance to be set to the optimal target values. The table includes the effect of the internal 18.5 kΩ feedback resistor, and minimizes the RMS error to input impedance target (Z_I) and overall gain.

At higher gains, R_M increases to larger values, and the resistor is excluded from the circuit. The resulting input impedance of the network is resistor R_G. From that point, R_F simply increases to get higher gains, thereby rapidly reducing the SSBW. However, below a gain of –5 V/V, the inverting design with the values shown in Table 8-3 holds a more constant SSBW versus the noninverting mode (see Figure 6-26).