SLOS930C November   2015  – October 2024 THS4541-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: (Vs+) – Vs– = 5 V
    6. 6.6 Electrical Characteristics: (Vs+) – Vs– = 3 V
    7. 6.7 Typical Characteristics: 5-V Single Supply
    8. 6.8 Typical Characteristics: 3-V Single Supply
    9. 6.9 Typical Characteristics: 3-V to 5-V Supply Range
  8. 7 Parameter Measurement Information
    1. 7.1 Example Characterization Circuits
    2. 7.2 Frequency-Response Shape Factors
    3. 7.3 I/O Headroom Considerations
    4. 7.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances
    5. 7.5 Noise Analysis
    6. 7.6 Factors Influencing Harmonic Distortion
    7. 7.7 Driving Capacitive Loads
    8. 7.8 Thermal Analysis
  9. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Terminology and Application Assumptions
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Differential I/O
      2. 8.3.2 Power-Down Control Pin ( PD)
        1. 8.3.2.1 Operating the Power Shutdown Feature
      3. 8.3.3 Input Overdrive Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation from Single-Ended Sources to Differential Outputs
        1. 8.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion
        2. 8.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversion
        3. 8.4.1.3 Resistor Design Equations for the Single-Ended to Differential Configuration of the FDA
        4. 8.4.1.4 Input Impedance for the Single-Ended to Differential FDA Configuration
      2. 8.4.2 Differential-Input to Differential-Output Operation
        1. 8.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. 8.4.2.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Designing Attenuators
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Interfacing to High-Performance ADCs
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 TINA Simulation Model Features
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGT|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Factors Influencing Harmonic Distortion

As shown in the swept frequency harmonic distortion plots, the THS4541-Q1 provides extremely low distortion at lower frequencies. In general, FDA output harmonic distortion mainly relates to the open-loop linearity in the output stage corrected by the loop gain at the fundamental frequency. As the total load impedance decreases (including the effect of the feedback resistor elements in parallel for loading purposes), the output-stage, open-loop linearity degrades, increasing the harmonic distortion, as illustrated in Figure 6-16 and Figure 6-34. As the output voltage swings increase, very fine-scale, open-loop, output-stage nonlinearities increase, also degrading the harmonic distortion, as illustrated in Figure 6-14 and Figure 6-32. Conversely, decreasing the target output voltage swings drops the distortion terms rapidly. For harmonic-distortion testing, 2 VPP is used as a nominal swing because this value represents a typical ADC, full-scale, differential input range.

Increasing the gain acts to decrease the loop gain, resulting in the increasing harmonic distortion terms, as illustrated in Figure 6-18 and Figure 6-36. One advantage to the capacitive compensation for the attenuator design (described in the Section 9.2.1 typical application example) is that the noise gain is shaped up with frequency to achieve a crossover at an acceptable phase margin at higher frequencies. This compensation holds the loop gain high at frequencies lower than the noise-gain zero, improving distortion in these lower bands.

Anything that moves the output pin voltage swings close to clipping into the supplies rapidly degrades harmonic distortion. Output clipping can occur from either absolute differential swing, or the swing can be moved closer to the supplies with the common-mode control. This effect is illustrated in Figure 6-17 and Figure 6-35.

The THS4541-Q1 does an exceptional job of converting from single-ended inputs to differential outputs with very low harmonic distortions. External resistors of 1% tolerance are used in characterization with good results. Imbalancing the feedback divider ratios does not degrade distortion directly. Imbalanced feedback ratios convert common-mode inputs to differential mode at the outputs with the gain described in the Section 7.4 section.