SBOS778D April   2016  – April 2021 THS4551

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Companion Devices
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: (VS+) – (VS–) = 5 V
    6. 7.6 Electrical Characteristics: (VS+) – (VS–) = 3 V
    7. 7.7 Typical Characteristics: (VS+) – (VS–) = 5 V
    8. 7.8 Typical Characteristics: (VS+) – (VS–) = 3 V
    9. 7.9 Typical Characteristics: 3-V to 5-V Supply Range
  8. 8 Parameter Measurement Information
    1. 8.1 Example Characterization Circuits
    2. 8.2 Output Interface Circuit for DC-Coupled Differential Testing
    3. 8.3 Output Common-Mode Measurements
    4. 8.4 Differential Amplifier Noise Measurements
    5. 8.5 Balanced Split-Supply Versus Single-Supply Characterization
    6. 8.6 Simulated Characterization Curves
    7. 8.7 Terminology and Application Assumptions
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Differential Open-Loop Gain and Output Impedance
      2. 9.3.2 Setting Resistor Values Versus Gain
      3. 9.3.3 I/O Headroom Considerations
      4. 9.3.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation from Single-Ended Sources to Differential Outputs
        1. 9.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversions
        2. 9.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversions
      2. 9.4.2 Operation from a Differential Input to a Differential Output
        1. 9.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. 9.4.2.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
      3. 9.4.3 Input Overdrive Performance
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Noise Analysis
      2. 10.1.2 Factors Influencing Harmonic Distortion
      3. 10.1.3 Driving Capacitive Loads
      4. 10.1.4 Interfacing to High-Performance Precision ADCs
      5. 10.1.5 Operating the Power Shutdown Feature
      6. 10.1.6 Designing Attenuators
      7. 10.1.7 The Effect of Adding a Feedback Capacitor
    2. 10.2 Typical Applications
      1. 10.2.1 An MFB Filter Driving an ADC Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Differential Transimpedance Output to a High-Grade Audio PCM DAC Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
      3. 10.2.3 ADC3k Driver with a 2nd-Order RLC Interstage Filter Application
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Thermal Analysis
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Board Layout Recommendations
    2. 12.2 Layout Example
    3. 12.3 EVM Board
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 TINA-TI Simulation Model Features
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Electrical Characteristics: (VS+) – (VS–) = 3 V

at TA ≈ 25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise noted); see Figure 8-1 for a gain of 1-V/V test circuit
PARAMETERTEST CONDITIONSMINTYPMAXUNITTEST
LEVEL(1)
AC PERFORMANCE
SSBWSmall-signal bandwidthVOUT = 20 mVPP, G = 1, peaking (< 1.0 dB)150MHzC
VOUT = 20 mVPP, G = 280C
VOUT = 20 mVPP, G = 1014C
GPBGain-bandwidth productVOUT = 20 mVPP, G = 100130MHzC
LSBWLarge-signal bandwidthVOUT = 1 VPP, G = 145MHzC
Bandwidth for 0.1-dB flatnessVOUT = 1 VPP, G = 114MHzC
SRSlew rate(2)VOUT = 1 VPP, FPBW, G = 1110V/µsC
tR, tFRise and fall timeVOUT = 0.5-V step, G = 1, input tR = 4 ns7.0nsC
tSETTLESettling timeTo 0.1%, VOUT = 0.5-V step, input tR = 4 ns, G = 135nsC
To 0.01%, VOUT = 0.5-V step, input tR = 4 ns, G = 155C
Overshoot and undershootVOUT = 0.5-V step, G = 1, input tR = 4 ns7%C
HD2Second-order harmonic distortionf = 100 kHz, VOUT = 2 VPP, G = 1, RL = 1 kΩ–128dBcC
f = 100 kHz, VOUT = 4 VPP, G = 1, RL = 1 kΩ–127C
HD3Third-order harmonic distortionf = 100 kHz, VOUT = 2 VPP, G = 1, RL = 1 kΩ–139dBcC
f = 100 kHz, VOUT = 4 VPP, G = 1, RL = 1 kΩ–125C
Input voltage noisef > 500 Hz, 1/f < 150 Hz3.4nV/√ HzC
Input current noisef > 20 kHz, 1/f < 10 kHz0.5pA/√ HzC
Overdrive recovery timeG = 2, 2X output overdrive, dc coupled100nsC
Closed-loop output impedancef = 100 kHz (differential), G = 10.02ΩC
DC PERFORMANCE(5)
AOLOpen-loop voltage gain±2-V differential to 1-kΩ differential load100120dBA
Internal feedback trace resistanceTA = 25°C, RGT only (pins 11-1, 10-4)3.03.454.7ΩA
TA = –40°C to +125°C, temperature drift50mΩ/°CB
Internal feedback trace resistance mismatchTA = 25°C, RGT only (pins 11-1, 10-4)(6)–10.051ΩA
TA = –40°C to +125°C, temperature drift50µΩ/°CB
VIOInput-referred offset voltageTA = 25°C–175±40175µVA
TA = 0°C to +70°C–225265B
TA = –40°C to +85°C–295295B
TA = –40°C to +125°C–295375B
Input offset voltage drift(3)TA = –40°C to +125°C (DGK package)–2.0±0.452.0µV/°CB
TA = –40°C to +125°C (RUN package)–1.7±0.41.7B
TA = –40°C to +125°C (RGT package)–1.8±0.41.8B
IIBInput bias current
(positive current out of node)		TA = 25°C1.01.5µAA
TA = 0°C to +70°C1.73B
TA = –40°C to +85°C1.80B
TA = –40°C to +125°C2.0B
Input bias current drift(3)TA = –40°C to +125°C23.35.5nA/°CB
IOSInput offset currentTA = 25°C–50±1050nAA
TA = 0°C to +70°C–5763B
TA = –40°C to +85°C–6867B
TA = –40°C to +125°C–6878B
Input offset current drift(3)TA = –40°C to +125°C (DGK package)–280±70280pA/°CB
TA = –40°C to +125°C (RGT and RUN package)–120±20120B
INPUT
Common-mode input, low> 87-dB CMRR at input range limitsTA = 25°C(VS–) – 0.2(VS–) – 0.1VA
TA = –40°C to +125°C(VS–) – 0.1VS–B
Common-mode input, high> 87-dB CMRR at input range limitsTA = 25°C(VS+) – 1.2(VS+) –1.1VA
TA = –40°C to +125°C(VS+) – 1.3(VS+) –1.2B
CMRRCommon-mode rejection ratioInput pins at [(VS+) – (VS–)] / 290110dBA
Input impedance differential modeInput pins at [(VS+) – (VS–)] / 2100 || 1.2kΩ || pFC
OUTPUT
VOLOutput voltage, lowTA = 25°C(VS–) + 0.2(VS–) + 0.21VA
TA = –40°C to +125°C(VS–) + 0.2(VS–) + 0.22B
VOHOutput voltage, highTA = 25°C(VS+) – 0.21(VS+) – 0.2VA
TA = –40°C to +125°C(VS+) – 0.22(VS+) – 0.2B
Continuous output current±1.5 V, RL = 40 Ω,
VOCM offset < ±20 mV		TA = 25°C±35±40mAA
±1.3 V, RL = 40 Ω,
VOCM offset < ±20 mV		TA = –40°C to +125°C±30B
Linear output current±1.5 V, RL = 50 Ω,
AOL > 80 dB		TA = 25°C±28±35mAA
±1.1 V, RL = 50 Ω,
AOL > 80 dB		TA = –40°C to +125°C±20B
POWER SUPPLY
Specified operating voltage2.735.4VB
IQQuiescent operating currentTA ≈ 25°C(7), VS+ = 3 V1.241.311.40mAA
TA = –40°C to +125°C, VS+ = 3 V0.961.84B
dIQ/dTQuiescent current temperature coefficientVS+ = 3 V2.03.45.0µA/°CB
±PSRRPower-supply rejection ratioEither supply pin to differential VOUT90105dBA
POWER-DOWN
Enable voltage thresholdSpecified on above (VS–) + 1.15 V(VS–) + 1.15VA
Disable voltage thresholdSpecified off below (VS–) + 0.55 V(VS–) + 0.55VA
Disable pin bias currentPD = VS– → VS+–100±10100nAB
IQ(PD)Power-down quiescent current–215µAA
tONTurn-on time delayTime from PD = low to VOUT = 90% of final value750nsC
tOFFTurn-off time delayTime from PD = low to VOUT = 10% of final value150nsC
OUTPUT COMMON-MODE VOLTAGE (VOCM) CONTROL(4) (See Figure 8-5)
SSBWSmall-signal bandwidthVOCM = 100 mVPP at the control pin40MHzC
LSBWLarge-signal bandwidthVOCM = 1 VPP at the control pin8MHzC
SRSlew rate(2)From 1-VPP LSBW12V/µsC
Output common-mode noiseVOCM pin driven from low impedance, f ≥ 2 kHz15nV/√ Hz
GainVOCM control pin input to output average voltage (see Figure 8-5)0.9970.9991.001V/VA
DC output balance (differential mode to common-mode output)VOUT = ±1 V85dBC
Output balanceSSBWVOUT = 100 mVPP (output balance drops –3 dB from the 85-dB dc level)300kHzC
LSBWVOUT = 1 VPP (output balance drops –3 dB from the 85-dB dc level)300C
Input bias current–100±10100nAA
Input impedance150 || 7kΩ || pFC
Default voltage offset from
[(VS+) – (VS–)] / 2		VOCM pin open–12±212mVA
VOCM pin open, TA = –40°C to +125°C153555µA/°CB
OUTPUT COMMON-MODE VOLTAGE (VOCM) CONTROL (continued)
CM VOSCommon-mode offset voltageVOCM input driven to [(VS+) – (VS–)] / 2TA = 25°C–5.0±15.0mVA
TA = 0°C to +70°C–5.255.5B
TA = –40°C to +85°C–5.75.6B
TA = –40°C to +125°C–5.76.0B
Common-mode offset voltage drift(3)VOCM input driven to [(VS+) – (VS–)] / 2–10±210µV/°CB
Common-mode loop supply headroom to negative supply< ±15-mV shift from midsupply CM VOSTA = 25°C0.55VA
TA = 0°C to +70°C0.6B
TA = –40°C to +85°C0.65B
TA = –40°C to +125°C0.7B
Common-mode loop supply headroom to positive supply< ±15-mV shift from midsupply CM VOSTA = 25°C1.2VA
TA = 0°C to +70°C1.25B
TA = –40°C to +85°C1.3B
TA = –40°C to +125°C1.3B
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at TA ≈ 25°C. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
(2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (VPP / √ 2) × 2π × f–3dB.
(3) Input offset voltage drift, input bias current drift, and input offset current drift are the mean ±1-sigma values calculated by taking measurements at the maximum-range ambient temperature end points, computing the difference, and dividing by the temperature range. Maximum drift specifications are set by mean ±4 σ on the device distributions tested over a –40°̊C to +125°̊C ambient temperature range. Drift is not specified by final ATE testing or QA sample test.
(4) Specifications are from input VOCM pin to differential output average voltage.
(5) Currents out of pin are treated as a positive polarity (with exception of the power-supply pin currents).
(6) Trace mismatch measurement is dominated by the variation in contactor resistance. Internal mismatch is less than 0.1 Ω.
(7) TA = 25°C and ICC ≈ 1.31 mA. The test limit is expanded for the ATE ambient range of 22°C to 32°C with a 4-µA/°C ICC temperature coefficient considered; see Figure 11-1.