SBOSA51 December   2020 THS4567

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: Differential TIA Mode, ICM loop enabled
    6. 6.6 Electrical Characteristics: FDA operation, ICM loop disabled
    7. 6.7 Typical Characteristics: (VS+) – (VS–) = 5 V
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Main Amplifier
      2. 7.3.2 Output Common-Mode Control
      3. 7.3.3 Input Common-Mode Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Differential Transimpedance Amplifier Mode
      3. 7.4.3 Fully Differential Amplifier (FDA) Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Noise Analysis
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure (THS4567 in TIA Mode)
        1. 8.2.2.1 OPA Mode Configuration
      3. 8.2.3 Application Curves
    3. 8.3 Differential TIA with 0-V Biased Photodiode
    4. 8.4 Differential AC Coupled TIA
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout Recommendations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3 Feature Description

The THS4567 architecture features three main building blocks:

  1. A high open loop gain differential I/O main amplifier.
  2. An output common-mode control error amplifier that sets the common-mode of the differential outputs of the main amplifier.
  3. An input common-mode control error amplifier that sets the common-mode of the differential inputs of the main amplifier, independent of the output common-mode.