SBOS974F August   2019  – December 2024 THS6222

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics VS = 12 V
    6. 5.6 Electrical Characteristics VS = 32 V
    7. 5.7 Timing Requirements
    8. 5.8 Typical Characteristics: VS = 12 V
    9. 5.9 Typical Characteristics: VS = 32 V
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Common-Mode Buffer
      2. 6.3.2 Thermal Protection and Package Power Dissipation
      3. 6.3.3 Output Voltage and Current Drive
      4. 6.3.4 Breakdown Supply Voltage
      5. 6.3.5 Surge Test Results
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Broadband PLC Line Driving
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
    3. 7.3 Best Design Practices
      1. 7.3.1 Do
      2. 7.3.2 Do Not
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
        1. 7.5.1.1 Wafer and Die Information
      2. 7.5.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGT|16
  • YS|0
  • RHF|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Revision History

Changes from Revision E (October 2024) to Revision F (December 2024)

  • Added language for PLC standards for SEO in Applications Go
  • Added language for PLC standards for SEO in Description Go
  • Updated front page image, Functional Block Diagram, and Figures 6-5, 6-7, 7-1, 7-2, and 7-5 to fix incorrect pin swap and labelsGo

Changes from Revision D (April 2021) to Revision E (October 2024)

  • Updated last Features bullet to clarify compatibility with THS6212Go
  • Deleted maximum junction temperature continuous operation, long-term reliability from Absolute Maximum Ratings Go
  • Updated drop-in replacement text in Overview sectionGo

Changes from Revision C (November 2020) to Revision D (April 2021)

  • Updated the wrong pin diagram image that was tagged incorrectly during system migrationGo

Changes from Revision B (April 2020) to Revision C (November 2020)

  • Updated the numbering format for tables, figures, and cross-references throughout the document Go
  • Added VQFN (16) package to the Device Information tableGo
  • Updated the RHF package in the Pin Configuration and Functions sectionGo
  • Added the RGT package in the Pin Configuration and Functions sectionGo

Changes from Revision A (December 2019) to Revision B (April 2020)

  • Added wafer sale package and BODY SIZE (NOM) to the Device Information table Go
  • Added the YS die bondpad and functionsGo
  • Updated Table 1 BIAS-1 and BIAS-2 Logic TableGo
  • Added Wafer and Die Information sectionGo

Changes from Revision * (August 2019) to Revision A (December 2019)

  • Changed device status from advance information to production data Go