SLLSF32C November   2018  – March 2019 THVD1419 , THVD1429

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      THVD1419 and THVD1429 Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 ESD Ratings [IEC]
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Power Dissipation
    7. 7.7 Electrical Characteristics
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 Electrostatic Discharge (ESD) Protection
      2. 9.3.2 Electrical Fast Transient (EFT) Protection
      3. 9.3.3 Surge Protection
      4. 9.3.4 Failsafe Receiver
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Data Rate and Bus Length
        2. 10.2.1.2 Stub Length
        3. 10.2.1.3 Bus Loading
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
    2. 13.2 Third-Party Products Disclaimer
    3. 13.3 Related Links
    4. 13.4 Receiving Notification of Documentation Updates
    5. 13.5 Community Resources
    6. 13.6 Trademarks
    7. 13.7 Electrostatic Discharge Caution
    8. 13.8 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.8 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Driver: THVD1419
tr, tf Differential output rise / fall time  RL = 54 Ω, CL = 50 pF, see Figure 12 300 500 ns
tPHL, tPLH Propagation delay 200 450 ns
tSK(P) Pulse skew, |tPHL – tPLH| 40 ns
tPHZ, tPLZ Disable time 20 50 ns
tPZH, tPZL Enable time RE = 0 V, see Figure 13 and Figure 14 60 250 ns
RE = VCC, see Figure 13 and Figure 14 3 11 µs
Receiver: THVD1419
tr, tf Output rise / fall time  CL = 15 pF, see Figure 15 14 20 ns
tPHL, tPLH Propagation delay 30 50 ns
tSK(P) Pulse skew, |tPHL – tPLH| 7 ns
tPHZ, tPLZ Disable time 35 45 ns
tPZH(1), tPZL(1), tPZH(2), tPZL(2), Enable time DE = VCC, see Figure 16 80 120 ns
DE = 0 V, see Figure 17 5 14 µs
Driver: THVD1429
tr, tf Differential output rise / fall time RL = 54 Ω, CL = 50 pF, see Figure 12 9 16 ns
tPHL, tPLH Propagation delay 12 25 ns
tSK(P) Pulse skew, |tPHL – tPLH| 6 ns
tPHZ, tPLZ Disable time 18 40 ns
tPZH, tPZL Enable time RE = 0 V, see Figure 13 and Figure 14 16 40 ns
RE = VCC, see Figure 13 and Figure 14 2.8 11 µs
Receiver: THVD1429
tr, tf Output rise / fall time CL = 15 pF, see Figure 15 2 6 ns
tPHL, tPLH Propagation delay 12 45 ns
tSK(P) Pulse skew, |tPHL – tPLH| 6 ns
tPHZ, tPLZ Disable time 14 28 ns
tPZH(1), tPZL(1), tPZH(2), tPZL(2), Enable time DE = VCC, see Figure 16 75 110 ns
DE = 0 V, see Figure 17 4.8 14 µs