SLLSFO2B December   2022  – March 2024 THVD2410V , THVD2412V , THVD2450V , THVD2452V

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  ESD Ratings [IEC]
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Power Dissipation
    7. 5.7  Electrical Characteristics
    8. 5.8  Switching Characteristics_250 kbps
    9. 5.9  Switching Characteristics_1 Mbps
    10. 5.10 Switching Characteristics_20 Mbps
    11. 5.11 Switching Characteristics_50 Mbps
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 ±70 V Fault Protection
      2. 7.3.2 Integrated IEC ESD and EFT Protection
      3. 7.3.3 Driver Overvoltage and Overcurrent Protection
      4. 7.3.4 Enhanced Receiver Noise Immunity
      5. 7.3.5 Receiver Fail-Safe Operation
      6. 7.3.6 Low-Power Shutdown Mode
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Data Rate and Bus Length
        2. 8.2.1.2 Stub Length
        3. 8.2.1.3 Bus Loading
        4. 8.2.1.4 Transient Protection
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.3 Application Curves

GUID-20221205-SS0I-FT6S-1XNC-VDHVSBXDWDQH-low.png
50% duty square wave on D pin at 250 kbps
SLR = VIO RL = 54 Ω  DE = VIO
Figure 8-8 THVD2410V Waveforms at VCC = 5 V
GUID-20221205-SS0I-MM5L-DCZH-SMCK5J3KDKGW-low.png
Random (PRBS7) data on D pin at 50 Mbps
SLR = GND RL = 54 Ω  DE = VIO
Figure 8-10 THVD2450V Waveforms at VCC = 5 V
GUID-20221205-SS0I-KZBG-WXLG-CQ7X2VJDKCSF-low.png
A pin given ±200mV VID with DC offset of 1.5 V
RE = GND B pin at 1.5 V 
Figure 8-12 THVD2450V Receiver Waveform with ±200 mV VID
GUID-20221205-SS0I-XQNQ-D90J-XVQWV56HC1SL-low.png
50% duty square wave on D pin at 250 kbps
SLR = VIO RL = 54 Ω  DE = VIO
Figure 8-9 THVD2410V Waveforms at VCC = 3.3 V
GUID-20221205-SS0I-JT7X-JLR1-XRP3LL5L8MC3-low.png
Random (PRBS7) data on D pin at 50 Mbps
SLR = GND RL = 54 Ω  DE = VIO
Figure 8-11 THVD2450V Waveforms at VCC = 3.3 V