The TIC12400 is an advanced Multiple Switch Detection Interface (MSDI) device designed to detect external switch statuses. The TIC12400 supports 24 direct inputs, with 10 inputs configurable to monitor digital I/O switches. 6 wetting current settings can be programmed for each input to support different application scenarios. The TIC12400 features an integrated 10-bit ADC to monitor multi-position analog switches and a comparator to monitor digital switches independently of the MCU. The device supports wake-up operation on all switch inputs to eliminate the need to keep the MCU active continuously, thus reducing power consumption of the system. The TIC12400 supports 2 modes of operations: continuous and polling mode. In continuous mode, wetting current is supplied continuously. In polling mode, wetting current is turned on periodically to sample the input status based on a programmable timer, thus the system power consumption is significantly reduced. The TIC12400 also offers various fault detection and diagnostic features for improved system robustness.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TIC12400 | TSSOP (38) | 9.70 mm x 4.40 mm |
DATE | REVISION | NOTES |
---|---|---|
September 2017 | * | Initial release. |
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PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | IN13 | I/O | Ground switch monitoring input with current source |
2 | IN14 | I/O | Ground switch monitoring input with current source |
3 | IN15 | I/O | Ground switch monitoring input with current source |
4 | IN16 | I/O | Ground switch monitoring input with current source |
5 | IN17 | I/O | Ground switch monitoring input with current source |
6 | IN18 | I/O | Ground switch monitoring input with current source |
7 | IN19 | I/O | Ground switch monitoring input with current source |
8 | IN20 | I/O | Ground switch monitoring input with current source |
9 | AGND | P | Ground for analog circuitry |
10 | IN21 | I/O | Ground switch monitoring input with current source |
11 | IN22 | I/O | Ground switch monitoring input with current source |
12 | IN23 | I/O | Ground switch monitoring input with current source |
13 | IN0 | I/O | Ground/VSUPPLY switch monitoring input with configurable current sink or source. |
14 | IN1 | I/O | Ground/VSUPPLY switch monitoring input with configurable current sink or source. |
15 | CS | I | Active-low input. Chip select from the master for the SPI Interface. |
16 | SCLK | I | Serial clock output from the master for the SPI Interface |
17 | SI | I | Serial data input for the SPI Interface. |
18 | SO | O | Serial data output for the SPI Interface |
19 | VDD | P | 3.3 V to 5.0 V logic supply for the SPI communication. The SPI I/Os are not fail-safe protected: VDD needs to be present during any SPI traffic to avoid excessive leakage currents and corrupted SPI I/O logic levels. |
20 | CAP_A | I/O | External capacitor connection for the analog LDO. Use capacitance value of 100nF. |
21 | RESET | I | Keep RESET low for normal operation and drive RESET high and release it to perform a hardware reset of the device. The RESET pin is connected to ground via a 1MΩ pull-down resistor. If not used, the RESET pin shall be grounded to avoid any accidental device reset due to coupled noise onto this pin. |
22 | CAP_Pre | I/O | External capacitor connection for the pre-regulator. Use capacitance value of 1μF. |
23 | CAP_D | I/O | External capacitor connection for the digital LDO. Use capacitance value of 100nF. |
24 | INT | O | Open drain output. Pulled low (internally) upon change of state on the input or occurrence of a special event. |
25 | IN2 | I/O | Ground/VSUPPLY switch monitoring input with configurable current sink or source. |
26 | IN3 | I/O | Ground/VSUPPLY switch monitoring input with configurable current sink or source. |
27 | IN4 | I/O | Ground/VSUPPLY switch monitoring input with configurable current sink or source. |
28 | DGND | P | Ground for digital circuitry |
29 | IN5 | I/O | Ground/VSUPPLY switch monitoring input with configurable current sink or source. |
30 | IN6 | I/O | Ground/VSUPPLY switch monitoring input with configurable current sink or source. |
31 | IN7 | I/O | Ground/VSUPPLY switch monitoring input with configurable current sink or source. |
32 | IN8 | I/O | Ground/VSUPPLY switch monitoring input with configurable current sink or source. |
33 | IN9 | I/O | Ground/VSUPPLY switch monitoring input with configurable current sink or source. |
34 | IN10 | I/O | Ground switch monitoring input with current source |
35 | IN11 | I/O | Ground switch monitoring input with current source |
36 | IN12 | I/O | Ground switch monitoring input with current source |
37 | VS | P | Power supply input pin. |
38 | VS | P | Power supply input pin. |
--- | EP | P | Exposed Pad. The exposed pad is not electrically connected to AGND or DGND. Connect EP to the board ground to achieve rated thermal and ESD performance. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input voltage | VS, INT | -0.3 | 40 | V |
VDD, SCLK, SI, SO, CS, RESET | -0.3 | 6 | V | |
IN0- IN23 | -24 | 40 | V | |
CAP_Pre | -0.3 | 5.5 | V | |
CAP_A | -0.3 | 5.5 | V | |
CAP_D | -0.3 | 2 | V | |
Operating junction temperature, TJ, VS = 18 V | -40 | 125 | °C | |
Operating junction temperature, TJ, VS = 24 V | -40 | 95 | °C | |
Storage temperature, Tstg | -55 | 155 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | All pins | ±2000 | V |
Pins IN0-IN23(2) | ±4000 | ||||
Charged-device model (CDM), per JEDEC specification JESD-C101(1) | All pins | ±500 | |||
Corner pins (pin 1, 19, 20 and 38) | ±750 | ||||
Contact discharge per IEC61000-4-2 contact discharge (3)(4) | Pins IN0-IN23v | ±8000 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VS | Power supply voltage, TA = -40 °C to 105 °C | 6.5 | 18 | V | ||
Power supply voltage, TA = -40 °C to 85 °C | 6.5 | 24 | V | |||
VDD | Logic supply voltage | 3.0 | 5.5 | V | ||
V/INT | INT pin voltage | 0 | 35 | V | ||
VINX | IN0 to IN23 input voltage | 0 | 35 | V | ||
VRESET | RESET pin voltage | 0 | 5.5 | V | ||
VSPI_IO | SPI input/output logic level | 0 | VDD | V | ||
fSPI | SPI communication frequency | 20(1) | 4M | Hz | ||
TA | Operating free-air temperature, VS = 18 V | -40 | 102 | °C | ||
TA | Operating free-air temperature, VS = 24 V | -40 | 85 | °C |
THERMAL METRIC(1) | TIC10024-Q1 | UNIT | |
---|---|---|---|
DCP (TSSOP) | |||
38 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 33.6 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 18.4 | °C/W |
RθJB | Junction-to-board thermal resistance | 15.2 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.5 | °C/W |
ψJB | Junction-to-board characterization parameter | 15.0 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 1.2 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
POWER SUPPLY | |||||||
IS_CONT | Continuous mode VS power supply current | Continuous mode, IWETT= 10 mA, all switches open, no active comparator operation, no unserviced interrupt | 5.6 | 7 | mA | ||
IS_POLL_COMP_25 | Polling mode VS power supply average current | TA= 25° | Polling mode, tPOLL= 64 ms, tPOLL_ACT= 128 µs, all switches open, IWETT= 10 mA, no unserviced interrupt | 68 | 100 | µA | |
IS_POLL_COMP_85 | TA= -40° to 85°C | 68 | 110 | µA | |||
IS_POLL_COMP | TA= -40° to 105°C | 68 | 170 | µA | |||
IS_RESET | Reset mode VS power supply current | Reset mode, VRESET= VDD. VS= 12 V, all switches open, TA=25°C | 12 | 17 | µA | ||
IS_IDLE_25 | VS power supply average current in idle state | TRIGGER bit in CONFIG register = logic 0, TA= 25°C, no unserviced interrupt | 50 | 75 | µA | ||
IS_IDLE_85 | TRIGGER bit in CONFIG register = logic 0, TA= -40°C to 85°C, no unserviced interrupt | 50 | 95 | µA | |||
IS_IDLE | TRIGGER bit in CONFIG register = logic 0, TA= -40°C to 125°C, no unserviced interrupt | 50 | 145 | µA | |||
IDD | Logic supply current from VDD | SCLK = SI = 0 V, CS = INT = VDD, no SPI communication | 1.5 | 10 | µA | ||
VPOR_R | Power on reset (POR) voltage for VS | Threshold for rising VS from device OFF condition resulting in INT pin assertion and a flagged POR bit in the INT_STAT register | 3.85 | 4.5 | V | ||
VPOR_F | Threshold for falling VS from device normal operation to reset mode and loss of SPI communication | 1.95 | 2.8 | V | |||
VOV_R | Over-voltage (OV) condition for VS | Threshold for rising VS from device normal operation resulting in INT pin assertion and a flagged OV bit in the INT_STAT register | 35 | 40 | V | ||
VOV_HYST | Over-voltage (OV) condition hysteresis for VS | 1 | 3.5 | V | |||
VUV_R | Under-voltage (UV) condition for VS | Threshold for rising VS from under-voltage condition resulting in INT pin assertion and a flagged UV bit in the INT_STAT register | 3.85 | 4.5 | V | ||
VUV_F | Threshold for falling VS from under-votlage condition resulting in INT pin assertion and a flagged UV bit in the INT_STAT register | 3.7 | 4.4 | V | |||
VUV_HYST | Under-voltage (UV) condition hysteresis for VS(1) | 75 | 275 | mV | |||
VDD_F | Threshold for falling VDD resulting in loss of SPI communication | 2.5 | 2.9 | V | |||
VDD_HYST | Valid VDD voltage hysteresis | 50 | 150 | mV | |||
WETTING CURRENT ACCURACY (DIGITAL SWITCHES, MAXIMUM RESISTANCE VALUE WITH SWITCH CLOSED ≤ 100Ω , MINIMUM RESISTANCE VALUE WITH SWITCH OPEN ≥ 5000 Ω) | |||||||
IWETT (CSO) | Wetting current accuracy for CSO (switch closed) | 1 mA setting | 6.5 V ≤ VS ≤ 35 V | 0.84 | 1 | 1.14 | mA |
2 mA setting | 1.71 | 2 | 2.32 | ||||
5 mA setting | 4.3 | 5 | 5.6 | ||||
10 mA setting | 8.4 | 10 | 11.4 | ||||
15 mA setting | 12.5 | 15 | 17 | ||||
IWETT (CSI) | Wetting current accuracy for CSI (switch closed) | 1 mA setting | 0.75 | 1.1 | 2.05 | ||
2 mA setting | 1.6 | 2.2 | 3.3 | ||||
5 mA setting | 4.3 | 5.6 | 7.1 | ||||
10 mA setting | 9.2 | 11.5 | 13.4 | ||||
15 mA setting | 13.7 | 16.5 | 19.2 | ||||
VCSI_DROP_OPEN | Voltage drop from INx pin to AGND across CSI (switch open) | 10 mA setting, RSW= 5kΩ | 6.5 V ≤ VS ≤ 35V | 1.7 | V | ||
15 mA setting, RSW= 5kΩ | 1.7 | ||||||
VCSI_DROP_CLOSED | Voltage drop from INx pin to ground across CSI (switch closed) | 2mA setting, IIN= 1mA | 6.5 V ≤ VS ≤ 35V | 1.2 | V | ||
5mA setting, IIN= 1mA or 2mA | 1.3 | V | |||||
10mA setting, IIN= 1mA, 2mA, or 5mA | 1.5 | V | |||||
15mA setting, IIN= 1mA, 2mA, 5mA, or 10mA | 2.1 | V | |||||
LEAKAGE CURRENTS | |||||||
IIN_LEAK_OFF | Leakage current at input INx when channel is disabled | 0 V ≤ VINx ≤ VS , channel disabled (EN_INx register bit= logic 0) | -4 | 5.3 | µA | ||
IIN_LEAK_OFF_25 | 0 V ≤ VINx ≤ VS , channel disabled (EN_INx register bit= logic 0), TA = 25°C | -0.5 | 0.5 | ||||
IIN_LEAK_0mA | Leakage current at input INx when wetting current setting is 0mA | 0 V ≤ VINx ≤ 6 V, 6.5 V ≤ VS ≤ 35 V , IWETT setting = 0 mA | -110 | 110 | µA | ||
µA | |||||||
IIN_LEAK_LOSS_OF_GND | Leakage current at input INx under loss of GND condition | VS = 24 V, 0 V ≤ VINx ≤ 24 V, all grounds (AGND, DGND, and EP) = 24 V, VDD shorted to the grounds(1) | -5 | µA | |||
IIN_LEAK_LOSS_OF_VS | Leakage current at input INx under loss of VS condition | 0 V ≤ VINx ≤ 24 V, VS shorted to the grounds = 0 V, VDD = 0 V | 5 | µA | |||
LOGIC LEVELS | |||||||
V/INT_L | INT output low voltage | I/INT = 2 mA | 0.35 | V | |||
I/INT = 4 mA | 0.6 | ||||||
VSO_L | SO output low voltage | ISO = 2 mA | 0.2VDD | V | |||
VSO_H | SO output high voltage | ISO = -2 mA | 0.8VDD | V | |||
VIN_L | SI, SCLK, and CS input low voltage | 0.3VDD | V | ||||
VIN_H | SI, SCLK, and CS input high voltage | 0.7VDD | V | ||||
VRESET_L | RESET input low voltage | 0.8 | V | ||||
VRESET_H | RESET input high voltage | 1.6 | V | ||||
RRESET_25 | RESET pin internal pull-down resistor | VRESET = 0 to 5.5V, TA = 25°C | 0.85 | 1.25 | 1.7 | MΩ | |
RRESET | VRESET = 0 to 5.5V, TA = –40° to 105°C | 0.2 | 2.1 | ||||
COMPARATOR PARAMETERS | |||||||
VTH_ COMP_2V | Comparator threshold for 2 V | THRES_COMP = 2 V | 1.85 | 2.25 | V | ||
VTH_ COMP_2p7V | Comparator threshold for 2.7 V | THRES_COMP = 2.7 V | 2.4 | 2.9 | V | ||
VTH_ COMP_3V | Comparator threshold for 3 V | THRES_COMP = 3 V | 2.85 | 3.3 | V | ||
VTH_ COMP_4V | Comparator threshold for 4 V | THRES_COMP = 4 V | 3.7 | 4.35 | V | ||
RIN, COMP | Comparator equivalent input resistance | THRES_COMP = 2 V | 30 | 130 | kΩ | ||
THRES_COMP = 2.7 V | 35 | 130 | |||||
THRES_COMP = 3 V | 35 | 105 | |||||
THRES_COMP = 4 V | 43 | 95 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
SWITCH MONITORING, INTERRUPT, STARTUP AND RESET | ||||||
tPOLL_ACT | Polling active time accuracy | Polling mode | -12% | 12% | ||
tPOLL | Polling time accuracy | Polling mode | -12% | 12% | ||
tCOMP | Comparator detection time | 18 | µs | |||
tCCP_TRAN | Transition time between last input sampling and start of clean current | 20 | µs | |||
tCCP_ACT | Clean current active time | -12% | 12% | |||
tSTARTUP | Polling startup time | 200 | 300 | 400 | µs | |
tINT_ACTIVE | Active INT assertion duration | 1.5 | 2 | 2.5 | ms | |
tINT_INACTIVE | INT de-assertion duration during a pending interrupt | 3 | 4 | 5 | ms | |
tINT_IDLE | Interrupt idle time | 80 | 100 | 120 | µs | |
tRESET | Time required to keep the RESET pin high to successfully reset the device (no pending interrupt)(1) | 2 | µs | |||
tREACT | Delay between a fault event (OV, UV, TW, or TSD) to a high to low transition on the INT pin | See Figure 10 for OV example. | 20 | µs | ||
SPI INTERFACE | ||||||
tLEAD | Falling edge of CS to rising edge of SCLK setup time | 100 | ns | |||
tLAG | Falling edge of SCLK to rising edge of CS setup time | 100 | ns | |||
tSU | SI to SCLK falling edge setup time | 30 | ns | |||
tHOLD | SI hold time after falling edge of SCLK | 20 | ns | |||
tVALID | Time from rising edge of SCLK to valid SO data | 70 | ns | |||
tSO(EN) | Time from falling edge of CS to SO low-impedance | 60 | ns | |||
tSO(DIS) | Time from rising edge of CS to SO high-impedance | Loading of 1 kΩ to GND. See Figure 11. | 60 | ns | ||
tR | SI, CS, and SCLK signals rise time | 5 | 30 | ns | ||
tF | SI, CS, and SCLK signals fall time | 5 | 30 | ns | ||
tINTER_FRAME | Delay between two SPI communication (CS low) sequences | 1.5 | µs | |||
tCKH | SCLK High time | 120 | ns | |||
tCKL | SCLK Low time | 120 | ns | |||
tINITIATION | Delay between valid VDD voltage and initial SPI communication | 45 | µs |
TA = 25°C |
TA = 25°C |
I(WETT) = 2 mA | 6.5 V ≤ VS ≤ 35 V |
I(WETT) = 10 mA | 6.5 V ≤ VS ≤ 35 V |
VS = 12 V |
I(WETT) = 1 mA | 6.5 V ≤ VS ≤ 35 V |
I(WETT) = 5 mA | 6.5 V ≤ VS ≤ 35 V |
I(WETT) = 15 mA | 6.5 V ≤ VS ≤ 35 V |
The TIC12400 is an advanced 24-input Multiple Switch Detection Interface (MSDI) device designed to detect external mechanical switches status in an industrial system by acting as an interface between the switches and the low-voltage microcontroller. The TIC12400 is an integrated solution that replaces many discrete components and provides integrated protection, input serialization, and system wake-up capability.
The device monitors 14 switches to GND and 10 additional switches that can be programmed to be connected to either GND or VSUPPLY. It features SPI interface to report individual switch status and provides programmability to control the device operation. The TIC12400 features a 10-bit ADC, which is useful to monitor analog inputs, such as resistor coded switches, that have multiple switching positions. To monitor only digital switches, an integrated comparator can be used instead to monitor the input status. The device has 2 modes of operation: continuous mode and polling mode. The polling mode is a low-power mode that can be activated to reduce current drawn in the system by only turning on the wetting current for a small duty cycle to detect switch status changes. An interrupt is generated upon detection of switch status change and it can be used to wake up the microcontroller to bring the entire system back to operation.
The VS supply provides power to the entire chip and the TIC12400 is designed to operate with VS ranging from 6.5 V to 35 V.
The VDD supply is used to determine the logic level on the SPI communication interface, source the current for the SO driver, and sets the pull-up voltage for the CS pin. It can also be used as a possible external pull-up supply for the INT pin in addition to the VS and it shall be connected to a 3 V to 5.5 V logic supply. Removing VDD from the device disables SPI communications, but does not reset the register configurations.
When the device is powered up for the first time, the condition is called Power-On Reset (POR), which sets the registers to their default values and initializes the device state machine. The internal POR controller holds the device in a reset condition until VS has reached VPOR_R, at which the reset condition is released with the device registers and state machine initialized to their default values. After the initialization process is completed, the INT pin is asserted low to notify the microcontroller, and the register bit POR in the INT_STAT register is asserted to logic 1. The SPI flag bit POR is also asserted at the SPI output (SO).
During device initialization, some factory settings are programmed into the device to allow accurate device operation. The device performs a self-check after the device is programmed to ensure correct settings are loaded. If the self-check returns an error, the CHK_FAIL bit in the INT_STAT register will be flagged to logic 1 along with the POR bit. If this very unlikely event occurs, the microcontroller is recommended to initiate software reset (see section Software Reset) to re-initialize the device to allow the correct settings to be re-programmed.
After device initialization, the TIC12400 is ready to be configured. The microcontroller can use SPI commands to program desired settings to the configuration registers. Once the device configuration is completed, the microcontroller is required to set the bit TRIGGER in the CONFIG register to logic 1 in order to activate wetting current and start external switch monitoring.
After the switch monitoring starts, the configuration registers turn into read-only registers (with the exception of the TRIGGER, CRC_T, and RESET bits in the CONFIG register and all bits in the CCP_CFG1 register). If at any time the device setting needs to be re-configured, the microcontroller is required to first set the bit TRIGGER in the CONFIG register to logic 0 to stop wetting current and switch monitoring. The microcontroller can then program configuration registers to the desired settings. Once the re-configuration is completed, the microcontroller can set the TRIGGER bit back to logic 1 to re-start switch monitoring.
Note the cyclic redundancy check (CRC) feature stays accessible during switch monitoring, which allows the microcontroller to verify device settings at all time. Refer to section Cyclic Redundancy Check (CRC) for more details of the CRC feature.
There are 3 ways to reset the TIC12400 and re-initialize all registers to their default values:
The device is turned off and all register contents are lost if the VS voltage drops below VPOR_F. To turn the device back on, the VS voltage must be raised back above VPOR_R, as illustrated in Figure 12. The device then starts the initialization process as described in section Device Initialization .
Microcontroller can toggle the RESET pin to perform a hardware reset to the device. The RESET pin is internally pulled-down via a 1MΩ resistor and must be kept low for normal operation. When the RESET pin is toggled high, the device enters the reset state with most of the internal blocks turned off and consumes very little current of IS_RESET. Switch monitoring and SPI communications are stopped in the reset state, and all register contents are cleared. When RESET pin is toggled back low, all the registers are set to their default values and the device state machine is re-initialized, similar to a POR event. When the re-initialization process is completed, the INT pin is asserted low, and the interrupt register bit POR and the SPI status flag POR are both asserted to notify the microcontroller that the device has completed the reset process.
Note in order to successfully reset the device, the RESET pin needs to be kept high for a minimum duration of tRESET. The pin is required to be driven with a stable input (below VRESET_L for logic low or above VRESET_H for logic H) to prevent the device from accidental reset.
In addition to hardware reset, the microcontroller can also issue a SPI command to initiate software reset. This is triggered by setting the RESET bit in the register CONFIG to logic 1, which re- initialized the device with all registers set to their default value. When the re-initialization process is completed, the INT pin is asserted low, and the interrupt register bit POR and the SPI status flag POR are both asserted to notify the microcontroller that the device has completed the reset process.
During normal operation of a typical 12 V system, the VS voltage is usually quite stable and stays well above 12 V. However, the VS voltage might drops temporarily during certain operations. If the VS voltage drops below VUV_F, the TIC12400 enters the under-voltage (UV) condition since there is not enough voltage headroom for the device to accurately generate wetting currents. The following describes the behavior of the TIC12400 under UV condition:
Note the device resets as described in section VS Supply POR if the VS voltage drops below VPOR_F, .
When the VS voltage rises above VUV_R, the INT pin is asserted low to notify the microcontroller that the UV condition no longer exists. The UV bit in the register INT_STAT is flagged to logic 1 and the bit UV_STAT bit is de-asserted to logic 0 in the register IN_STAT_MISC to reflect the clearance of the UV condition. The device resumes operation using current register settings (regardless of the INT pin and SPI communication status) with polling restarted from the first enabled channel. The Switch State Change (SSC) interrupt is generated at the end of the first polling cycle and the detected switch status becomes the baseline switch status for subsequent polling cycles. The content of the INT_STAT register, once read by the microcontroller, is cleared, and the INT pin is released afterwards. .
The following diagram describes the TIC12400 operation at various different VS voltages. If the VS voltage stays above VUV_F (Case 1), the device stays in normal operation. If the VS voltage drops below VUV_F but stays above VPOR_F (Case 2), the device enters the UV condition. If VS voltage drops below VPOR_F (Case 3), the device resets and all register settings are cleared. The microcontroller is then required to re-program all the configuration registers in order to resume normal operation after the VS voltage recovers.
If VS voltage rises above VOV_R, the TIC12400 enters the over-voltage (OV) condition to prevent damage to internal structures of the device on the VS and INx pins. The following describes the behavior of the TIC12400 under OV condition:
When the VS voltage drops below VOV_R- VOV_HYST, the INT pin is asserted low to notify the microcontroller that the over-voltage condition no longer exists. The OV bit in the register INT_STAT is flagged to logic 1 and the bit OV_STAT bit is de-asserted to logic 0 in the register IN_STAT_MISC to reflect the clearance of the OV condition. The device resumes operation using current register settings (regardless of the INT pin and SPI communication status) with polling restarted from the first enabled channel. The Switch State Change (SSC) interrupt is generated at the end of the first polling cycle and the detected switch status becomes the baseline status for subsequent polling cycles. The content of the INT_STAT register, once read by the microcontroller, is cleared, and the INT pin is released afterwards.
IN0 to IN23 are inputs connected to external mechanical switches. All the inputs can sustain up to 40 V without being damaged. The switch status of each input, whether open or closed, is indicated by the status registers. Table 1 below describe various settings that can be configured for each input. Note some settings are shared between multiple inputs and it is required to first stop device operation by setting the TRIGGER bit low in the register CONFIG before making any configuration changes, as described in Device Trigger.
Input | Threshold | Wetting Current | Current Source (CSO) / Current Sink (CSI) | Supported Switch Type | ||
---|---|---|---|---|---|---|
Comparator Input Mode | ADC Input Mode | |||||
IN0 | THRES_COMP_IN0_IN3 | THRES0 to THRES7 | THRES_COM | WC_IN0_IN1 | CSO CSI |
Switch to GND Switch to VSUPPLY |
IN1 | THRES0 to THRES7 | CSO CSI |
Switch to GND Switch to VSUPPLY |
|||
IN2 | THRES0 to THRES7 | WC_IN2_IN3 | CSO CSI |
Switch to GND Switch to VSUPPLY |
||
IN3 | THRES0 to THRES7 | CSO CSI |
Switch to GND Switch to VSUPPLY |
|||
IN4 | THRES_COMP_IN4_IN7 | THRES0 to THRES7 | WC_IN4 | CSO CSI |
Switch to GND Switch to VSUPPLY |
|
IN5 | THRES0 to THRES7 | WC_IN5 | CSO CSI |
Switch to GND Switch to VSUPPLY |
||
IN6 | THRES0 to THRES7 | WC_IN6_IN7 | CSO CSI |
Switch to GND Switch to VSUPPLY |
||
IN7 | THRES0 to THRES7 | CSO CSI |
Switch to GND Switch to VSUPPLY |
|||
IN8 | THRES_COMP_IN8_IN11 | THRES0 to THRES7 | WC_IN8_IN9 | CSO CSI |
Switch to GND Switch to VSUPPLY |
|
IN9 | THRES0 to THRES7 | CSO CSI |
Switch to GND Switch to VSUPPLY |
|||
IN10 | THRES0 to THRES7 | WC_IN10 | CSO | Switch to GND | ||
IN11 | THRES0 to THRES7 | WC_IN11 | CSO | Switch to GND | ||
IN12 | THRES_COMP_IN12_IN15 | THRES2A THRES2B |
WC_IN12_13 | CSO | Switch to GND | |
IN13 | THRES2A THRES2B |
CSO | Switch to GND | |||
IN14 | THRES2A THRES2B |
WC_IN14_15 | CSO | Switch to GND | ||
IN15 | THRES2A THRES2B |
CSO | Switch to GND | |||
IN16 | THRES_COMP_IN16_IN19 | THRES2A THRES2B |
WC_IN16_17 | CSO | Switch to GND | |
IN17 | THRES2A THRES2B |
CSO | Switch to GND | |||
IN18 | THRES3A THRES3B THRES3C |
WC_IN18_19 | CSO | Switch to GND | ||
IN19 | THRES3A THRES3B THRES3C |
CSO | Switch to GND | |||
IN20 | THRES_COMP_IN20_IN23 | THRES3A THRES3B THRES3C |
WC_IN20_21 | CSO | Switch to GND | |
IN21 | THRES3A THRES3B THRES3C |
CSO | Switch to GND | |||
IN22 | THRES3A THRES3B THRES3C |
WC_IN22 | CSO | Switch to GND | ||
IN23 | THRES3A THRES3B THRES3C THRES8 THRES9 |
WC_IN23 | CSO | Switch to GND |
Among the 24 inputs, IN10 to IN23 are intended for monitoring only ground-connected switches and are connected to current sources. IN0 to IN9 can be programmed to monitor either ground-connected switches or supply-connected switches by configuring the CS_SELECT register. The default configuration of the IN0-IN9 inputs after POR is to monitor ground-connected switches (current sources are selected). To set an input to monitor supply-connected switches, set the corresponding bit to logic 1.
The TIC12400 has a built-in ADC and a comparator that can be used to monitor resistor coded switches or digital switches. Digital switch inputs have only two states, either open or closed, and can be adequately detected by a comparator. Resistor coded switches may have multiple positions that need to be detected, and an ADC is appropriate to monitor the different states. Each input of the TIC12400 can be individually programmed to use either a comparator or an ADC by configuring the appropriate bits in theMODE register depending on the knowledge of the external switch connections. The benefit of using a comparator instead of an ADC to monitor digital switches is its reduced polling time, which translates to overall power saving when the device operates in the low-power polling mode.
Comparator input mode is selected by default for all enabled inputs upon device reset.
The TIC12400 provides switch status monitoring for up to 24 inputs, but there might be circumstances in which not all inputs need to be constantly monitored. The microcontroller may choose to enable/disable monitoring of certain inputs by configuring the IN_EN register. Setting the corresponding bit to logic 0 to de-activates the wetting current source/sink and stops switch status monitoring for the input. Disabling monitoring of unused inputs reduce overall power consumption of the device.
All inputs are disabled by default upon device reset.
When an input is configured as comparator input mode, the threshold level for interrupt generation of can be programmed by setting the THRES_COMP register. The threshold level settings can be set to for each individual input groups and each group consist of 4 inputs. Four threshold levels are available: 2V, 2.7V, 3V, and 4V.
When an input is configured as ADC input mode, the threshold level for interrupt generation can be configured, up to 1023 different levels, by setting the THRES_CFG1 to THRES_CFG2 registers. One threshold level can be programmed individually for each of the input from IN0 to IN11. Additionally, one common threshold, shared between inputs IN0 to IN11, can be programmed by configuring the THRES_COM bits in register MATRIX. The common threshold acts independently from the threshold THRES0 to THRES7. Inputs IN12 to IN17 use 2 preset threshold levels (THRES2A and THRES2B). Inputs 18 to 22 use 3 preset threshold levels (THRES3A, THRES3B, and THRES3C). Input 23 uses 5 preset threshold levels (THRES3A, THRES3B, THRES3C, THRES8 and THRES9).
When multiple threshold settings are used for ADC inputs, the thresholds levels needs to be configured properly. Use the rules below (see Table 2) when setting up the threshold levels:
Input | Proper Threshold Configuration |
---|---|
IN12 to IN17 | THRES2B ≥ THRES2A |
IN18 to IN22 | THRES3C ≥ THRES3B ≥ THRES3A |
IN23 | THRES9 ≥ THRES8 ≥ THRES3C ≥ THRES3B ≥ THRES3A |
Caution should be used when setting up the threshold for switches that are connected externally to the supply as there are finite voltage drop (as high as VCSI_DROP for 10mA and 15mA settings) across the current sinks. Therefore, even for an open switch, then voltage on the INx pin can be as high as VCSI_DROP and the detection threshold shall be configured above it. It shall also be noted that a lower wetting current sink setting might not be stronger enough to pull the INx pin close to ground in the presence of a leaky open external switch, as illustrated in the diagram below (see Figure 14). In this example, the external switch, although in the open state, has large leakage current and can be modelled as an equivalent resistor (RDIRT) of 5kΩ. The 2mA current sink is only able to pull the INx pin voltage down to 2V, even the switch is in the open state.
It is possible to configure an input to ADC input mode, instead of comparator input mode, to monitor single-threshold digital switches. The following programming procedure is recommended under such configuration:
Input | Recommended Threshold Configuration |
---|---|
IN0 to IN11 | Configure the desired threshold to one of the settings from THRES0 to THRES7 and map it accordingly |
IN12 to IN17 |
|
IN18 to IN22 |
|
IN23 |
|
There are 6 different wetting current settings (0mA, 1mA, 2mA, 5mA, 10mA, and 15mA) that can be programmed by configuring the WC_CFG0 and WC_CFG1 registers. 0mA is selected by default upon device reset.
To monitor resistor coded switches, a lower wetting current setting (1 mA, 2 mA, or 5 mA) is generally desirable to get the resolution needed to resolve different input voltages while keeping them within the ADC full-scale range (0 V to 6 V). Higher wetting current settings (10mA and 15mA) are useful to clean switch contact oxidation that may form on the surface of an open switch contact. If switch contact cleaning is required for resistor coded switches, the clean current polling (CCP) feature can be activated to generate short cleaning pulses periodically using higher wetting current settings at the end of every polling cycle.
The accuracy of the wetting current has stronger dependency on the VS voltage when VS voltage is low. The lower the VS voltage falls, the more deviation on the wetting currents from their nominal values. Refer to IWETT (CSO) and IWETT (CSI) specifications for more details.
The INT pin is an active-low, open-drain output that asserts low when an event (switch input state change, temperature warning, over-voltage shutdown…etc) is detected by the TIC12400. An external pull-up resistor to VDD is needed on the INT pin (see Figure 15). If VDD supply is absent, the INT output is functional provided that it is pulled up to a different supply voltage. The INT pin can tolerate up to 40 V but is recommended to be kept below 35V for normal operation.
TIC12400 supports two configurable schemes for INT assertion: static and dynamic. The scheme can be adjusted by configuring the INT_CONFIG bit in the CONFIG register.
If the static INT assertion scheme is used (INT_CONFIG = 0 in the CONFIG register), the INT pin is asserted low upon occurrence of an event. The INT pin is released on the rising edge of CS only if a READ command has been issued to read the INT_STAT register while CS is low, otherwise the INT will be kept low indefinitely. The content of the INT_STAT interrupt register is latched on the first rising edge of SCLK after CS goes low for every SPI transaction, and the content is cleared upon a READ command issued to the INT_STAT register, as illustrated in Figure 16.
In some system implementation, an edge-triggered based microcontroller might potentially miss the INT assertion if it is configured to the static scheme, especially when the microcontroller is in the process of waking up. To prevent missed INT assertion and improve robustness of the interrupt behavior, the TIC12400 provides the option to use the dynamic assertion scheme for the INT pin. When the dynamic scheme is used (INT_CONFIG= 1 in the CONFIG register), the INT pin is asserted low for a duration of tINT_ACTIVE, and is de-asserted back to high if the INT_STAT register has not been read after tINT_ACTIVE has elapsed. The INT is kept high for a duration of tINT_INACTIVE, and is re-asserted low after tINT_INACTIVE has elapsed. TheINT pin continues to toggle until the INT_STAT register is read.
If the INT_STAT register is read when INT pin is asserted low, the INT pin is released on the READ command’s CS rising edge and the content of the INT_STAT register is also cleared, as shown in Figure 17. If the INT_STAT register is read when INT pin is de-asserted, the content of the INT_STAT register is cleared on the READ command’s CS rising edge, and the INT pin is not re-asserted back low, as shown in Figure 18.
The static INT assertion scheme is selected by default upon device reset. The INT pin assertion scheme can only be changed when bit TRIGGER is logic 0 in the CONFIG register.
Interrupt idle time (tINT_IDLE) is implemented in TIC12400 to:
When there is a pending interrupt event and the interrupt event is not masked, tINT_IDLE is applied after the READ command is issued to the INT_STAT register. If another event occurs during the interrupt idle time, the INT_STAT register content is updated instantly, but the INT pin is not asserted low until tINT_IDLE has elapsed. If another READ command is issued to the INT_STAT register during tINT_IDLE, the INT_STAT register content is cleared immediately, but the INT pin is not re-asserted back low after tINT_IDLE has elapsed. An example of the interrupt idle time is given below to illustrate the INT pin behavior under the static /INT assertion schemes:
When used together with external PNP transistors, the INT pin could also be used for wake-up purpose to activate a voltage regulator via its inhibit inputs (see Figure 20). This is especially useful for waking up a microcontroller in sleep mode. Before the wake-up, the VDD could be unavailable to the TIC12400 and the INT pin can be pulled up externally to the VS voltage. When an event (switch status change, temperature warning, or OV…etc) takes place, the INT pin will be asserted low to activate the voltage regulator, which in turn activates the microcontroller to enable the communication between the microcontroller and the TIC12400. The event information is stored inside the device interrupt register (INT_STAT) for the microcontrollers retrieval when the communication is reestablished.
The wake-up implementation is applicable only when the device is configured to use the static INT assertion scheme.
Each switch input can be programmed to enable or disable interrupt generation upon status change by configuring registers INT_EN_COMP1 to INT_EN_COMP2 (for comparator inputs) and INT_EN_CFG1 to INT_EN_CFG4 (for ADC inputs). Interrupt generation condition can be adjusted for THRES_COM (for IN0-IN11) by adjusting the IN_COM_EN bit in the MATRIX register.
The abovementioned registers can also be used to control interrupt generation condition based on the following settings:
Note interrupt generation from switch status change is disabled for all inputs by default upon device reset.
When monitoring the switch input status, an detection filter can be configured by setting the DET_FILTER bits in the CONFIG register to generate switch status change (SSC) interrupt only if the same input status (w.r.t the threshold) is sampled consecutively. This detection filter can be useful to debounce inputs during switch toggle event. Four different filtering schemes are available:
The default value of switch status is stored internally after the 1st detection cycle, even if detection filter (by configure the DET_FILTER in the CONFIG register) is used. An example is illustrated below with the assumption that DET_FILTER in register CONFIG is set to 11 (SSC interrupt generated if the input crosses threshold and the status is stable w.r.t. the threshold for at least 4 consecutive detection cycles). Assume switch status change is detected in the 3rd detection cycle and stays the same for the next 3 cycles.
Detection cycle | 1 | 2 | 3 | 4 | 5 | 6 |
---|---|---|---|---|---|---|
Event |
|
— | Switch status change detected | — | — |
|
Tthe detection filter applies to all enabled inputs regardless its input modes (ADC or comparator) selection. The detection filter counter is reset to 0 when the TRIGGER bit in the CONFIG register is de-asserted to logic 0. Upon device reset, the default setting for the detection filter is set to generating an SSC interrupt at every threshold crossing.
Note the detection filter does not apply to the common threshold THRES_COM.
With multiple switch inputs closed and high wetting current setting enabled, considerable power could be dissipated by the device and raise the device temperature. TIC12400 has integrated temperature monitoring and protection circuitry to prevent permanent device damage resulted from device overheating. Two types of temperature protection mechanisms are integrated in the device: Temperature Warning (TW) and Temperature Shutdown (TSD). The triggering temperatures and hysteresis are specified in Table 4 below:
Parameter | Min | Typ | Max | Unit |
---|---|---|---|---|
Temperature warning trigger temperature (TTW) | 130 | 140 | 155 | °C |
Temperature shutdown trigger temperature (TTSD) | 150 | 160 | 175 | °C |
Temperature hysteresis (THYS) for TTW and TTSD | 15 | °C |
When the device temperature goes above the temperature warning trigger temperature (TTW), the TIC12400 performs the following operations:
The INT pin is released and the INT_STAT register content is cleared on the rising edge of CS provided the INT_STAT register has been read during CS low. The TIC12400 continues to monitor the temperature, but does not issue further interrupts if the temperature continues to stay above TTW- THYS. The status bit TW_STAT in register IN_STAT_MISC continues to stay at logic 1 as long as the temperature warning condition exists.
If desired, the reduction of wetting current down to 2 mA setting (from 10 mA or 15 mA) can be disabled by setting the TW_CUR_DIS_CSO or TW_CUR_DIS_CSI bit in the CONFIG register to 1. The interrupt is still generated (INT asserted low and INT_STAT interrupt register content updated) when the temperature warning event occurs but the wetting current is not reduced. This setting applies to both the polling and continuous mode operation. Note if the feature is enabled, switch detection result might be impacted upon TTW event if the wetting current is reduced to 2mA from 10mA or 15mA.
When the temperature drops below TTW - THYS, the INT pin is asserted low (if released previously) to notify the microcontroller that the temperature warning condition no longer exists. The TW bit of the interrupt register INT_STAT is flagged logic 1. The TW_STAT bit in the IN_STAT_MISC register is de-asserted back to logic 0. The device resumes operation using the current programmed settings (regardless of the INT and CS status).
After the device enters TW condition, if the junction temperature continues to rise and goes above the temperature shutdown threshold (TTSD), the TIC12400 enters the Temperature Shutdown (TSD) condition and performs the following operations:
The INT pin is released and the INT_STAT register content is cleared on the rising edge of CS provided the INT_STAT register has been read during CS low. The TIC12400 continues to monitor the temperature, but does not issue further interrupts if the temperature continues to stay above TTSD- THYS. The status bit TSD_STAT in register IN_STAT_MISC continues to stay at logic 1 as long as the temperature shutdown condition exists.
When the temperature drops below TTSD - THYS, the INT pin is asserted low (if released previously) to notify the microcontroller that the temperature shutdown condition no longer exists. The TSD bit of the interrupt register INT_STAT is flagged logic 1. In the IN_STAT_MISC register, the TSD_STAT bit is de-asserted back to logic 0, while the TW_STAT bit stays at logic 1. The device resumes operation using the wetting current setting described in section Temperature Warning if the temperature stays above TTW - THYS. Note the polling restarts from the first enabled channel and the SSC interrupt is generated at the end of the first polling cycle. The detected switch status from the first polling cycle becomes the default switch status for subsequent polling.
The TIC12400 uses parity bit check to ensure error-free data transmission from/to the SPI master.
The device uses odd parity, for which the parity bit is set so that the total number of ones in the transmitted data on SO (including the parity bit) is an odd number (that is, Bit0 ⊕ Bit1 ⊕ ….⊕ Bit30 ⊕ Bit31⊕ Parity = 1).
The device also does odd parity check after receiving data on SI from the SPI master. If the total number of ones in the received data (including the parity bit) is an even number, the received data is discarded. The INT will be asserted low and the PRTY_FAIL bit in the interrupt register (INT_STAT) is flagged to logic 1 to notify the host that transmission error occurred. The PRTY_FAIL flag is also asserted during SPI communications.
The TIC12400 includes a CRC module to support redundancy checks on the configuration registers to ensure the integrity of data. The CRC calculation is based on the ITU-T X.25 implementation, and the CRC polynomial (0x1021) used is popularly known as CRC-CCITT-16 since it was initially proposed by the ITU-T (formerly CCITT) committee. The CRC calculation rule is defined as:
CRC Rule | Value |
---|---|
CRC result width | 16 bits |
Polynomial | x^16+ x^12+ x^5+1 (1021h) |
Initial (seed) value | FFFFh |
Input data reflected | No |
Result data reflected | No |
XOR value | 0000h |
The CRC calculation is done on all the configuration registers starting from register CONFIG and ending at register MODE. The device substitutes a “zero” for each reserved configuration register bit during the CRC calculation. The CRC calculation can be triggered by asserting the CRC_T bit in the CONFIG register. Once completed, the CRC_CALC interrupt bit in the INT_STAT register is asserted and an interrupt is issued, The 16-bit CRC calculation result is stored in the register CRC. This interrupt can be disabled by de-asserting the CRC_CALC_EN bit in the INT_EN_CFG0 register. It is important to avoid writing data to the configuration registers when the device is undergoing CRC calculations to prevent generation of any false calculation result.
The diagram below shows the block diagram of the CRC module. The module consists of 16 shift-registers and 3 exclusive-OR gates. The registers start with 1111-1111-1111-1111 (or FFFFh) and the module performs XOR action and shifts its content until the last bit of the register string is used. The final register’s content after the last data bit is the calculated CRC value of the data set and the content is stored in the CRC register.
Note the CRC_T bit is self-clearing after CRC calculation is completed. Logic 1 is used for CRC_T bit during CRC calculation.
The TIC12400 has 2 modes of operation: continuous mode, and polling mode. The following sections describe the two operation modes in details, as well as some of the advanced features that could be activated during normal operations.
In continuous mode, wetting current is continuously applied to each enabled input channel, and the status of each channel is sampled sequentially (starting from the IN0 to IN23). The TIC12400 monitors enabled inputs and issues an interrupt (if enabled) if switch status change event is detected. The wetting current setting for each input can be individually adjusted by configuring the WC_CFG0 and WC_CFG1 to the 0 mA, 1 mA, 2 mA, 5 mA, 10 mA, or 15 mA setting. Each input is monitored by either a comparator or an ADC depending on the setting of the input mode in the register MODE.
Figure 22 below illustrates an example of the timing diagram of the detection sequence in continuous mode. After the TRIGGER bit in register CONFIG is set to logic 1, it takes tSTARTUP to activate the wetting current for all enabled inputs. The wetting currents stay on continuously, while each input is routed to the ADC/comparator for sampling in a sequential fashion. After conversion/comparison is done for an input, the switch status (below or above detection threshold) is stored in registers (IN_STAT_COMP for comparator inputs and IN_STAT_ADC0 to IN_STAT_ADC1 for ADC inputs) to be used as the default state for subsequent detection cycles. The digital values (if the input is configured as ADC input mode) are stored inside the registers ANA_STAT0 toANA_STAT11. After the end of the first polling cycle, the INT pin is asserted low to notify the microcontroller that the default switch status is ready to be read. The SSC bit in INT_STAT register and the SPI status flag SSC are also asserted to logic 1. The polling cycle time (tPOLL) determines how frequently each input is sampled and can be configured in the register CONFIG.
The INT_STAT register is cleared and INT pin de-asserted if a SPI READ commanded is issued to the register. Note the interrupt is always generated after the 1st detection cycle (after the TRIGGER bit in register CONFIG is set to logic 1). In subsequent detection cycles, the interrupt is generated only if switch status change is detected.
No wetting current is applied to the inputs configured to the 0mA setting, although some biasing current (as specified by IIN_LEAK_0mA) may still flow in and out of the input. Threshold crossing monitoring is still performed for the input using the defined threshold(s). The 0mA setting is useful to utilize the integrated ADC or comparator to measure applied voltage on a specific input without getting affected by the device wetting current.
The polling mode can be activated to reduce current drawn to reduce heat dissipation. Unlike in the continuous mode, the current sources/sinks do not stay on continuously in the polling mode. Instead, they are turned on/off sequentially from IN0 to IN23 and cycled through each individual input channel. The microcontroller can be put to sleep to reduce overall system power. If a switch status change (SSC) is detected by the TIC12400, the INT pin (if enabled for the input channel) is asserted low (and the SSC bit in INT_STAT register and the SPI status flag SSC are also asserted to logic 1). The INT assertion can be used to wake up the system regulator, which in turn wakes up the microcontroller as described in section Microcontroller Wake-Up. The microcontroller can then use SPI communication to read the switch status information.
The polling is activated when the TRIGGER bit in the CONFIG register is set to logic 1. There are 2 different polling schemes that can be configured in TIC12400: standard polling and matrix polling.
In standard polling mode, wetting current is applied to each input for a pre-programmed polling active time set by the POLL_ACT_TIME bits in the CONFIG register between 64us and 2048 us. At the end of the wetting current application, the input voltage is sampled by the comparator (if input is configured as comparator input mode) or the ADC (if input is configured as ADC input mode). Each input is cycled through in sequential order from IN0 to IN23. Sampling is repeated at a frequency set by the POLL_TIME bits in the CONFIG register from 2ms to 4096ms. Wetting currents are applied to closed switches only during the polling active time; hence the overall system current consumption can be greatly reduced.
Similar to continuous mode, after the first polling cycle, the switch status of each input (below or above detection threshold) is stored internally in registers (IN_STAT_COMP for comparator inputs and IN_STAT_ADC0 to IN_STAT_ADC1 for ADC inputs) to be used as the default state for subsequent polling cycles. The digital values (if the input is configured as ADC input mode) are stored inside the registers ANA_STAT0 toANA_STAT11. The INT pin is asserted low to notify the microcontroller that the default switch status is ready to be read. The SSC bit in INT_STAT register and the SPI status flag SSC are also asserted to logic 1. The INT_STAT register is cleared and /INT pin de-asserted if a SPI READ commanded is issued to the register. Note the interrupt is always generated after the 1st polling cycle (after the TRIGGER bit in register CONFIG is set to logic 1). In subsequent polling cycles, the interrupt is generated only if switch status change is detected.
An example of the timing diagram of the polling mode operation is shown in Figure 23. Note in this example, IN1 is set to comparator input mode, while the other inputs are set to ADC input mode. As a result, the wetting current applied to IN2 is activated faster (tCOMP instead of tADC after IN1 wetting current turns off) to shorten the overall polling period. Shortened polling period translates to reduced overall power consumption for the system.
If the switch position changes between two active polling times, no interrupt will be generated and the status registers (IN_STAT_COMP for comparator inputs and IN_STAT_ADC0 to IN_STAT_ADC1 for ADC inputs) will not reflect such a change. An example is shown in Figure 24.
From IN4 to IN15, a special input switch matrix (see Figure 25) can be configured and monitored in addition to the standard switches to GND and VSUPPLY. This feature could be useful to monitor a special switch input configuration call Matrix, as required by some specific OEMs.
Three different matrix configurations are possible, and are defined by MATRIX bits in the MATRIX register. If the MATRIX bits are set to ‘00’, all inputs are treated as standard inputs with identical polling active time according to the POLL_ACT_TIME bits in the CONFIG register. Any settings other than ‘00’ for MATRIX bits causes the polling active time for the matrix inputs to be configured according to POLL_ACT_TIME_M bits in the MATRIX register. Inputs that are not part of the matrix configuration will be configured using the POLL_ACT_TIME bits in the CONFIG register. tPOLL_ACT_TIME_M should be configured properly to allow sufficient time for the current source/sink to charge/discharge the capacitors (if any) connected to the switch inputs.
Input | 4x4 matrix | 5x5 matrix | 6x6 matrix | |||
---|---|---|---|---|---|---|
Current Source Or Sink | Polling Active Time Setting | Current Source Or Sink | Polling Active Time Setting | Current Source Or Sink | Polling Active Time Setting | |
IN4 | CSI | POLL_ACT_TIME_M | CSI | POLL_ACT_TIME_M | CSI | POLL_ACT_TIME_M |
IN5 | CSI | CSI | CSI | |||
IN6 | CSI | CSI | CSI | |||
IN7 | CSI | CSI | CSI | |||
IN8 | Configurable to CSO or CSI | POLL_ACT_TIME | CSI | CSI | ||
IN9 | Configurable to CSO or CSI | Configurable to CSO or CSI | POLL_ACT_TIME | CSI | ||
IN10 | CSO | POLL_ACT_TIME_M | CSO | POLL_ACT_TIME_M | CSO | |
IN11 | CSO | CSO | CSO | |||
IN12 | CSO | CSO | CSO | |||
IN13 | CSO | CSO | CSO | |||
IN14 | CSO | POLL_ACT_TIME | CSO | CSO | ||
IN15 | CSO | CSO | POLL_ACT_TIME | CSO |
The TIC12400 implements a different polling scheme when matrix input is configured. After the polling sequence is started (by setting TRIGGER bit in CONFIG register to logic 1), the polling takes place within the matrix input group first before the rest of the standard inputs are polled. After the matrix inputs are polled, the switch status of each input combination (below or above detection threshold) is stored internally in registers IN_STAT_MATRIX0 and IN_STAT_MATRIX1, and it is used as the default state for subsequent matrix polling cycles. The standard inputs follow the same polling behavior as described in section Standard Polling. After the polling cycle (matrix+ standard) is completed, the INT pin is asserted low to notify the microcontroller that the default switch status is ready to be read. The SSC bit in the INT_STAT register and the SPI status flag SSC are also asserted to logic 1.
The INT_STAT register is cleared and INT pin de-asserted if a SPI READ commanded is issued to the register. Note the interrupt is always generated after the 1st complete polling cycle (after the TRIGGER bit in register CONFIG is set to logic 1). In subsequent polling cycles, the interrupt is generated only if switch status change is detected.
Note the following programming requirement when using the matrix polling:
CSO (IN10-IN15) | CSI (IN4-IN9) | Resulting wetting current |
---|---|---|
1 mA | 2 mA, 5 mA, 10 mA, 15 mA | 1 mA |
2 mA | 5 mA | 2 mA |
If higher wetting current is needed and TW event might be expected, the TW wetting current reduction feature needs to be disabled by setting TW_CUR_DIS_CSO or TW_CUR_DIS_CSI bit in the CONFIG register to 1.
Some programmability is removed when matrix polling mode is used, as listed below:
Figure 26 illustrates an example of the polling sequence for the 6x6 matrix input configuration:
Figure 27 illustrates an example of the polling sequence for the 5x5 matrix input configuration. Note the input IN9 and IN15 are included in the standard polling sequence.
Figure 28 illustrates an example of the polling sequence for the 4x4 matrix input configuration. Note inputs IN8, IN9, IN14, and IN15 are included in the standard polling sequence.
There are additional features that can be enabled during continuous and polling mode to increase robustness of device operation or provide more system information. These features are described in detail in the following sections:
To detect resistor coded switches or reduce overall power consumption of the chip, a lower wetting current setting might be desired. However, certain system design requires 10mA or higher cleaning current to clear oxide build-up on the mechanical switch contact surface when the current is applied to closed switches. A special type of polling, called the Clean Current Polling (CCP) can be used for this application.
If CCP is enabled, each polling cycle consists of two wetting current activation steps. The first step uses the wetting current setting configured in the WC_CFG0 and WC_CFG1 registers as in the continuous mode or polling mode. The second step (cleaning cycle) is activated simultaneously for all CCP enabled inputs tCCP_TRAN after the normal polling step of the last enabled input. Interrupt generation and INT pin assertion is not impacted by the clean current pulses.
The wetting current and its active time for the cleaning cycle can be configured in the CCP_CFG0 register. The cleaning cycle can be disabled, if desired, for each individual input by programming the CCP_CFG1 register. CCP is available for both continuous mode and the polling mode. To use the CCP feature, at least one input (standard or matrix) or the VS measurement has to be enabled.
Note that although CCP can be enabled in Matrix polling mode, it is not an effective way to clean the matrix switch contact, since the current supplied from the TIC12400 is divided and distributed across multiple matrix channels.
Figure 29 illustrates the operation of the CCP when the device is configured to the standard polling mode.
Figure 30 illustrates the operation of the CCP when the device is configured to the continuous mode:
The 10 mA and 15 mA wetting current settings are useful to clean oxide build-up on the mechanical switch contact surface when the switch changes state from open to close. After the switch is closed, it might be undesirable to keep the wetting current level at high level if only digital switches are monitored since it results in high current consumption and could potentially heat up the device quickly if multiple inputs are monitored. The wetting current auto-scaling feature help mitigate this issue.
When enabled (AUTO_SCALE_DIS_CSO or AUTO_SCALE_DIS_CSI bit = logic 0 in the WC_CFG1 register), wetting current is reduced to 2 mA from 10 mA or 15 mA setting after switch closure is detected. The threshold used to determine a switch closure is the threshold configured in the THRES_COMP register for inputs configured as comparator input mode. For inputs configured as ADC input mode, the threshold used to determine a switch closure depends on the input number, as described in Table 8 below:
Input | Threshold used to determine a switch closure |
---|---|
IN0-IN11 | Mapped threshold from THRES0 to THRES7 |
IN12 to IN17 | THRES2B |
IN18 to IN22 | THRES3C |
IN23 | THRES9 |
The current reduction takes place N cycles after switch closure is detected on an input, where N depends on the setting of the DET_FILTER bits in the CONFIG register:
The wetting current is adjusted back to the original setting of 10 mA or 15 mA N cycles after an open switch is detected, where N again depends on the DET_FILTER bit setting in the CONFIG register. Figure 31 depicts the behavior of the wetting current auto-scaling feature.
The wetting current auto-scaling only applies to 10 mA and 15 mA settings and is only available in continuous mode. If AUTO_SCALE_DIS_CSO or AUTO_SCALE_DIS_CSI bit is set to logic 1 in the WC_CFG1 registers, the wetting current stays at its original setting when a closed switch is detected. Power dissipation needs to be closely monitored when wetting current auto-scaling is disabled for multiple inputs as the device could heat up quickly when high wetting current settings are used. If the auto-scaling feature is disabled in continuous mode, total power dissipation can be calculated using Equation 1 below.
where IWETT (TOTOAL) is the sum of all wetting currents from all input channels. Increase in device junction temperature can be calculated based on P ×RθJA. The junction temperature has to be limited below TTSD for proper device operation. An interrupt will be issued when the junction temperature exceeds TTW or TTSD. For detailed description of the temperature monitoring, please refer to sections Temperature Warning (TW)and Temperature Shutdown (TSD).
When the TIC12400 is used to monitor resistor-coded switches, the level of VS supply voltage becomes very critical. If VS is not sufficiently high, the device might not have enough headroom to produce accurate wetting currents. This could impact the accuracy of the switch status monitoring. It is imperative for the microcontroller to have knowledge of the VS voltage on a constant basis in such a case.
Measurement of VS voltage is a feature in TIC12400 that can be enabled by setting the VS_MEAS_EN bit in register CONFIG to logic 1. If enabled, at the end of every detection/polling cycle, the voltage on the VS pin is sampled and converted by the ADC to an digital value. The conversion takes one extra tADC, and the converted value is recorded in the ANA_STAT12 register.
The VS measurement supports two different VS voltage ranges that can be configured by the VS_RATIO bit in the CONFIG register. By default (VS_RATIO = logic 0), the supported VS voltage range is from 6.5 V to 9 V, and VS voltage in excess of 9 V results in a saturated ADC raw code of 1023. This setting provides better measurement resolution at lower VS voltages. When VS_RATIO bit is set to logic 1, the supported VS voltage range is widened to 6.5V to 30V, and VS voltage in excess of 30 V results in a saturated ADC raw code of 1023. This setting allows wider measurement range but more coarse measurement resolution. It is important to adjust the detection thresholds accordingly depending on the VS voltage range configured.
Four different thresholds (VS0_THRES2A/B and VS1_THRES2A/B) can be programmed to have the TIC12400 notify the microcontroller when the VS voltage crosses the thresholds. The value of these thresholds can be programmed by configuring registers THRES_CFG0 to THRES_CFG3 and the mapping can be programmed by configuring registers THRESMAP_VS0_THRES2A/B and THRESMAP_VS1_THRES2A/B bits in the register THRESMAP_CFG2. When setting the thresholds, follow the rules in Table 9 below:
VS Threshold | Proper Threshold Configuration |
---|---|
VS0 | VS0_THRES2B ≥ VS0_THRES2A |
VS1 | VS1_THRES2B ≥ VS1_THRES2A |
After the VS measurement is enabled for the first time, the VS measurement interrupt is always generated (INT pin is asserted low, and the VS0 or VS1 bit in the INT_STAT register is flagged to logic 1) at the end of the first polling cycle to notify the microcontroller the initial VS measurement result is ready to be retrieved . The VS0_STAT and VS1_STAT bits from register IN_STAT_MISC indicate the status of the VS voltage with respect to the thresholds, and the ANA_STAT12 register stores the converted digital value of the VS voltage. The SPI status flag VS_TH is also asserted to logic 1 during SPI communications. Note the status detected in the first polling cycle becomes the baseline value of comparison for subsequent VS measurements and the interrupt will be generated only if threshold crossing is detected.
Similar to regular inputs, interrupt generation condition can be programmed by setting the VS_TH0_EN and VS_TH1_EN bits in the INT_EN_CFG4 register to the following settings:
Interrupt generation can also be disabled by setting VS_TH0_EN or VS_TH1_EN to logic 0 in register INT_EN_CFG4. Once disabled, VS voltage crossing does not flag the VS0 or VS1 bit in INT_STAT register and does not assert INT pin low. To only mask the INT pin from assertion (while keeping INT_STAT register updated), configure the VS1_EN and VS0_EN bits in register INT_EN_CFG0 to logic 0.
Note the VS measurement is only intended to be used as part of switch detection sequence to determine the validity of the switch detection states that are reported by the TIC12400. It is not intended to be used for standalone supply monitoring, such as monitoring cranking voltages, due to the potentially delayed response being part of the polling sequence. The VS measurement result is accurate for VS above 6.5V.
By default, the VS voltage measurement is disabled upon device reset.
When the TIC12400 is used to monitor safety-critical switches, it might be valuable for the microcontroller to have knowledge of the wetting current sources/ sinks operating status. This can be achieved by activating the wetting current diagnostic feature provided for inputs IN0 to IN3. IN0 and IN1 can be diagnosed for defective wetting current sources, while IN2 and IN3 can be diagnosed for failed current sinks.
The wetting current diagnostic feature can be activated by setting the WET_D_INx_EN bits in the CONFIG register to 1 for the desired inputs, where x can be 0, 1, 2, or 3. If activated, the TIC12400 checks the status of the wetting current sources/sinks for the configured input periodically as part of the polling sequence. If the wetting current is determined to be flawed, the TIC12400 pulls the INT pin low to notify the host and flag the WET_DIAG bit in the INT_STAT register to logic 1. The OI bit in the SPI flag is also asserted during SPI transactions. The microcontroller can then read bits IN0_D to IN3_D in register IN_STAT_MISC to learn more information on which wetting current source/sink is defective.
The wetting current diagnostic is not performed for inputs that are disabled (IN_EN_x bit = 0 in the IN_EN register) from polling, even if the feature if activated for those inputs. Also, it is critical to configure the current source/sink appropriately (CSO for IN0/IN1 and CSI for IN2/IN3) and program the input to ADC input mode before activating the wetting current diagnostic feature to avoid false interrupt from generation. The wetting current diagnostic feature can be performed regardless of the states of external switches, and it is available in both continuous mode and the polling mode.
Figure 32 shows an example of the feature carried out in a typical polling sequence. In this example, it can be observed that the wetting current is activated for duration of tPOLL_ACT+ tADC for each input diagnosed. After IN3 is diagnosed, normal polling sequence resumes and the wetting current is activated for tPOLL_ACT for the rest of the inputs. The diagnostic is not executed on input IN2 in this example since it is disabled.
In addition to the wetting current diagnostic, another diagnostic feature, the ADC self-diagnostic, can be enabled to monitor the integrity of the internal ADC.
The ADC self-diagnostic feature is activated by setting the ADC_DIAG_T bit in the CONFIG register to logic 1. Once enabled, the TIC12400 periodically sends a test voltage to the ADC. The conversion result is stored in the ADC_SELF_ANA bits in the register ANA_STAT12 and it is compared with a pre-defined code to determine whether the conversion is performed properly. If an error is detected, the TIC12400 pulls the INT pin low to notify the host and flag the ADC_DIAG bit in the INT_STAT to logic 1. The bit ADC_D in register IN_STAT_MISC is updated with the result from the self-diagnostic. The ADC self-diagnostic feature is available in both continuous mode and the polling mode.
The SPI interface communication consists of the 4 pins: CS, SCLK, SI, and SO. The interface can work with SCLK frequency up to 4MHz.
The system microcontroller selects the TIC12400 to receive communication using the CS pin. With the CS pin in a logic LOW state, command words may be sent to the TIC12400 via the serial input (SI) pin, and the device information can be retrieved by the microcontroller via the serial output (SO) pin. The falling edge of the CS enables the SO output and latches the content of the interrupt register INT_STAT. The microcontroller may issue a READ command to retrieve information stored in the registers. Rising edge on the CS pin initiates the following operations:
To avoid any corrupted data, it is essential the HIGH-to-LOW and LOW-to-HIGH transitions of the CS signal occur only when SCLK is in a logic LOW state. A clean CS signal is needed to ensure no incomplete SPI words are sent to the device. The CS pin should be externally pulled up to VDD by a 10-kΩ resistor.
The system clock (SCLK) pin clocks the internal shift register of the TIC12400. The SI data is latched into the input shift register on the falling edge of the SCLK signal. The SO pin shifts the device stored information out on the rising edge of SCLK. The SO data is available for the microcontroller to read on the falling edge of SCLK.
False clocking of the shift register must be avoided to ensure validity of data and it is essential the SCLK pin be in a logic LOW state whenever CS makes any transition. Therefore, it is recommended that the SCLK pin gets pulled to a logic LOW state as long as the device is not accessed and CS is in a logic HIGH state. When the CS is in a logic HIGH state, any signal on the SCLK and SI pins will be ignored and the SO pin remains as a high impedance output. Refer to Figure 33 and Figure 34 for examples of typical SPI read and write sequence.
The SI pin is used for serial instruction data input. SI information is latched into the input register on the falling edge of the SCLK. To program a complete word, 32 bits of information must be enter into the device. The SPI logic counts the number of bits clocked into the IC and enables data latching only if exactly 32 bits have been clocked in. In case the word length exceeds or does not meet the required length, the SPI_FAIL bit of the INT_STAT register is asserted to logic 1 and the INT pin will be asserted low. The data received is considered invalid. Note the SPI_FAIL bit is not flagged if SCLK is not present.
The SO pin is the output from the internal shift register. The SO pin remains high-impedance until the CS pin transitions to a logic LOW state. The negative transition of CS enables the SO output driver and drive the SO output to the HIGH state (by default). The first positive transition of SCLK makes the status data bit 32 available on the SO pin. Each successive positive clock makes the next status data bit available for the microcontroller to read on the falling edge of SCLK. The SI/SO shifting of the data follows a first-in, first-out scheme, with both input and output words transferring the most significant bit (MSB) first.
The following diagrams depict the SPI communication sequence during read and write operations for
TIC12400.
The Read/Write bit (bit 31) of the SI bus needs to be set to logic 0 for a READ operation. The 6-bits address of the register to be accessed follows next on the SI bus. The content from bit 24 to bit 1 does not represent valid command for a read operation and will be ignored. The LSB (bit 0) is the parity bit used to detect communication errors.
On the SO bus, the status flags will be outputted from the TIC12400, followed by the data content in the register that was requested. The LSB is the parity bit used to detect communication errors.
Note there are several test mode registers (not shown in this ASD) used in the TIC12400 in addition to the normal functional registers, and a READ command to these test registers returns the register content. If a READ command is issued to an invalid register address, the TIC12400 will return all 0’s.
The Read/Write bit (bit 31) on the SI bus needs to be set to 1 for a write operation. The 6-bits address of the register to be accessed follows next on the SI bus. Note the register needs to be a writable configuration register, or otherwise, the command will be ignored. The content from bit 24 to bit 1 represents the data to be written to the register. The LSB (bit 0) is the parity bit used to detect communication errors.
On the SO bus, the status flags will be outputted from the TIC12400, followed by the previous data content of the same register being written to. The previous data content of the register is latched after the full register address is decoded in the SI command (after bit 25 is transmitted). The new data will replace the previous data content at the end of the SPI transaction if the SI write is a valid command (valid register address and no SPI/parity error). If the write command is invalid, the new data will be ignored and the previous data content of the register stays. The LSB is the parity bit used to detect communication errors.
Note there are several test mode registers (not shown in this ASD) used in the TIC12400 in addition to the normal functional registers. A WRITE command to these test registers have no effect on the register content, though the register content is returned on the SO output. If a WRITE command is issued to an invalid register address, the SO output would returns all 0’s.
The status flags are output from SO during every READ or WRITE SPI transaction to indicate system conditions. These bits do not belong to an actual register, but the content is mirrored from the interrupt register INT_STAT. A READ command executed on the INT_STAT would clear both the bits inside the register and the status flag. The following table describes the information that can be obtained from each SPI status flag:
Symbol | Name | Description |
---|---|---|
POR | Power-on Reset | This flag mirrors the POR bit in the interrupt register INT_STAT and it indicates, if set to 1, that a reset event has occurred. This bit is asserted after a successful power-on=reset, hardware reset or software reset. Refer to section Device Reset for more details. |
SPI_FAIL | SPI Error | This flag mirrors the SPI_FAIL bit in the interrupt register INT_STAT and it indicates, if set to 1, that the last SPI Slave In (SI) transaction is invalid. To program a complete word, 32 bits of information must be entered into the device. The SPI logic counts the number of bits clocked into the IC and enables data latching only if exactly 32 bits have been clocked in. In case the word length exceeds or does not meet the required size, the SPI_FAIL bit, which mirrors its value to this SPI_FAIL status flag, of the interrupt register INT_STAT will be set to 1 and the INT pin will be asserted low. The data received will be considered invalid. Once the INT_STAT register is read, its content will be cleared on the rising edge of CS. The SPI_FAIL status flag, which mirrors the SPI_FAIL bit in the INT_STAT register, will also be de-asserted. Note the SPI_FAIL bit is not flagged if SCLK is not present. |
PRTY_FAIL | Parity Fail | This flag mirrors the PRTY_FAIL bit in the interrupt register INT_STAT and it indicates, if set to 1, that the last SPI Slave In (SI) transaction has a parity error. The device uses odd parity. If the total number of ones in the received data (including the parity bit) is an even number, the received data is discarded. The INT will be asserted low and the PRTY_FAIL bit in the interrupt register (INT_STAT) is flagged to logic 1, and the PRTY_FAIL status flag, which mirrors the PRTY_FAIL bit in the INT_STAT register, is also set to 1. Once the INT_STAT register is read, its content will be cleared on the rising edge of CS. The PRTY_FAIL status flag, which mirrors the PRTY_FAIL bit in the INT_STAT register, will also be de-asserted. |
SSC | Switch State Change | This flag mirrors the SSC bit in the interrupt register INT_STAT and it indicates, if set to 1, that one or more switch input crossed threshold(s). To determine the origin of the state change, the microcontroller can read the content of registers IN_STAT_COMP (if input is set to comparator input mode), IN_STAT_ADC0 to IN_STAT_ADC1 (if input is set to ADC input mode), or IN_STAT_MATRIX0 to IN_STAT_MATRIX1 (if input is set to matrix input). Once the interrupt register (INT_STAT) is read, its content will be cleared on the rising edge of CS. The SSC status flag, which mirrors the SSC bit in the INT_STAT register, will also be de-asserted. |
VS_TH | VS Threshold Crossing | This flag is set to 1 if either VS0 or VS1 bit in the interrupt register INT_STAT is flagged to 1. It indicates the VS voltage crosses thresholds defined by VS0_THRES2A, VS0_THRES2B, VS1_THRES2A, or VS1_THRES2A. To determine the origin of the threshold crossing, the microcontroller can read register bits VS0_STAT and VS1_STAT in the register IN_STAT_MISC. Once the interrupt register (INT_STAT) is read, its content will be cleared on the rising edge of CS, and the VS_TH status flag will also be de-asserted. |
TEMP | Temperature event | This flag is set to 1 if either TW or TSD bit in the interrupt register INT_STAT is flagged to 1. It indicates a Temperature Warning (TW) event or a Temperature Shutdown (TSD) event has occurred. It is also flagged to 1 if a Temperature Warning (TW) event or a Temperature Shutdown (TSD) event cleared. The interrupt register INT_STAT should be read to determine which event occurred. The SPI master can also read the IN_STAT_MISC register to get information on the temperature status of the device. Once the interrupt register (INT_STAT) is read, its content will be cleared on the rising edge of CS, and the TEMP status flag will also be de-asserted. |
OI | Other Interrupt | Other interrupt include interrupts such as OV, UV, CRC_CALC. WET_DIAG, ADC_DIAG and CHK_FAIL. This flag will be asserted 1 when any of the abovementioned bits is flagged in the interrupt register INT_STAT. The interrupt register INT_STAT should be read to determine which event(s) occurred. The SPI master can also read the IN_STAT_MISC register to get information on the latest status of the device. Once the INT_STAT register is read, its content will be cleared on the rising edge of CS, and the OI status flag will also be de-asserted. |
Table 11 lists the memory-mapped registers for the TIC12400. All register offset addresses not listed in Table 11 should be considered as reserved locations and the register contents should not be modified.
Offset | Type | Reset | Acronym | Register Name | Section |
---|---|---|---|---|---|
1h | R | 20h | DEVICE_ID | Device ID Register | Go |
2h | RC | 1h | INT_STAT | Interrupt Status Register | Go |
3h | R | FFFFh | CRC | CRC Result Register | Go |
4h | R | 0h | IN_STAT_MISC | Miscellaneous Status Register | Go |
5h | R | 0h | IN_STAT_COMP | Comparator Status Register | Go |
6h-7h | R | 0h | IN_STAT_ADC0, IN_STAT_ADC1 | ADC Status Register | Go |
8h-9h | R | 0h | IN_STAT_MATRIX0, IN_STAT_MATRIX1 | Matrix Status Register | Go |
Ah-16h | R | 0h | ANA_STAT0- ANA_STAT12 | ADC Raw Code Register | Go |
17h-19h | — | — | RESERVED | RESERVED | — |
1Ah | R/W | 0h | CONFIG | Device Global Configuration Register | Go |
1Bh | R/W | 0h | IN_EN | Input Enable Register | Go |
1Ch | R/W | 0h | CS_SELECT | Current Source/Sink Selection Register | Go |
1Dh-1Eh | R/W | 0h | WC_CFG0, WC_CFG1 | Wetting Current Configuration Register | Go |
1Fh-20h | R/W | 0h | CCP_CFG0, CCP_CFG1 | Clean Current Polling Register | Go |
21h | R/W | 0h | THRES_COMP | Comparator Threshold Control Register | Go |
22h-23h | R/W | 0h | INT_EN_COMP1, INT_EN_COMP2 | Comparator Input Interrupt Generation Control Register | Go |
24h | R/W | 0h | INT_EN_CFG0 | Global Interrupt Generation Control Register | Go |
25h-28h | R/W | 0h | INT_EN_CFG1- INT_EN_CFG4 | ADC Input Interrupt Generation Control Register | Go |
29h-2Dh | R/W | 0h | THRES_CFG0- THRES_CFG4 | ADC Threshold Control Register | Go |
2Eh- 30h | R/W | 0h | THRESMAP_CFG0- THRESMAP_CFG2 | ADC Threshold Mapping Register | Go |
31h | R/W | 0h | Matrix | Matrix Setting Register | Go |
32h | R/W | 0h | Mode | Mode Setting Register | Go |
DEVICE_ID is shown in Figure 35 and described in Table 12.
Return to Summary Table.
This register represents the device ID of the TIC12400.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 |
RESERVED | |||||||||||
R-0h | |||||||||||
11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MAJOR | MINOR | |||||||||
R-0h | R-2h | R-0h |
LEGEND: R = Read only |
INT_STAT is shown in Figure 36 and described in Table 13.
Return to Summary Table.
This register records the information of the event as it occurs in the device. A READ command executed on this register clears its content and resets the register to its default value. The INT pin is released at the rising edge of the CS pin from the READ command.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CHK_FAIL | ADC_DIAG | WET_DIAG | VS1 | VS0 | CRC_CALC | |
R-0h | RC-0h | RC-0h | RC-0h | RC-0h | RC-0h | RC-0h | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UV | OV | TW | TSD | SSC | PRTY_FAIL | SPI_FAIL | POR |
RC-0h | RC-0h | RC-0h | RC-0h | RC-0h | RC-0h | RC-0h | RC-1h |
LEGEND: R = Read only; RC = Read to clear |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
23-14 | RESERVED | R | 0h |
RESERVED |
13 | CHK_FAIL | RC | 0h |
0h = Default factory setting is successfully loaded upon device initialization or the event status got cleared after a READ command was executed on the INT_STAT register. 1h = An error is detected when loading factory settings into the device upon device initialization. During device initialization, factory settings are programmed into the device to allow proper device operation. The device performs a self-check after the device is programmed to diagnose whether correct settings are loaded. If the self-check returns an error, the CHK_FAIL bit is flagged to logic 1 along with the POR bit. The host controller is then recommended to initiate a software reset (see section Software Reset) to re-initialize the device and allow correct settings to be re-programmed. |
12 | ADC_DIAG | RC | 0h |
0h = No ADC self-diagnostic error is detected or the event status got cleared after a READ command was executed on the INT_STAT register. 1h = ADC self-diagnostic error is detected. The ADC Self-Diagnostic feature (see section ADC Self-Diagnostic) can be activated to monitor the integrity of the internal ADC. The ADC_DIAG bit is flagged to logic 1 if an ADC error is diagnosed. |
11 | WET_DIAG | RC | 0h |
0h = No wetting current error is detected, or the event status got cleared after a READ command was executed on the INT_STAT register. 1h = Wetting current error is detected. The Wetting Current Diagnostic feature (see section Wetting Current Diagnostic) can be activated to monitor the integrity of the internal current sources or sinks. The WET_DIAG bit is flagged to logic 1 if an wetting current error is diagnosed. |
10 | VS1 | RC | 0h |
0h = No VS voltage state change occurred with respect to VS1_THRES2A or VS1_THRES2B or the status got cleared after a READ command was executed on the INT_STAT register. 1h = VS voltage state change occurred with respect to VS1_THRES2A or VS1_THRES2B. The VS1 interrupt bit indicates whether VS voltage state change occurred with respect to thresholds VS1_THRES2A and VS1_THRES2B if the VS Measurement feature (see section VS Measurement) is activated. |
9 | VS0 | RC | 0h |
0h = No VS voltage state change occurred with respect to VS0_THRES2A or VS0_THRES2B or the status got cleared after a READ command was executed on the INT_STAT register. 1h = VS voltage state change occurred with respect to VS0_THRES2A 10or VS0_THRES2B. The VS0 interrupt bit indicates whether VS voltage state change occurred with respect to thresholds VS0_THRES2A and VS0_THRES2B if the VS Measurement feature (see section VS Measurement) is activated. |
8 | CRC_CALC | RC | 0h |
0h = CRC calculation is running, not started, or was acknowledged after a READ command was executed on the INT_STAT register. 1h = CRC calculation is finished. CRC calculation (see section Cyclic Redundancy Check (CRC)) can be triggered to make sure correct register values are programmed into the device. Once the calculation is completed, the CRC_CALC bit is flagged to logic 1 to indicate completion of the calculation, and the result can then be accessed from the CRC (offset = 3h) register. |
7 | UV | RC | 0h |
0h = No under-voltage condition occurred or cleared on the VS pin, or the event status got cleared after a READ command was executed on the INT_STAT register. 1h = Under-voltage condition occurred or cleared on the VS pin. When the UV bit is flagged to logic 1, it indicates the Under-Voltage (UV) event has occurred. The bit is also flagged to logic 1 when the event clears. For more details about the UV operation, please refer to section VS under-voltage (UV) condition. |
6 | OV | RC | 0h |
0h = No over-voltage condition occurred or cleared on the VS pin, or the event status got cleared after a READ command was executed on the INT_STAT register. 1h = Over-voltage condition occurred or cleared on the VS pin. When the OV bit is flagged to logic 1, it indicates the Over-Voltage (OV) event has occurred. The bit is also flagged to logic 1 when the event clears. For more details about the OV operation, please refer to section VS over-voltage (OV) condition. |
5 | TW | RC | 0h |
0h = No temperature warning event occurred or the event status got cleared after a READ command was executed on the INT_STAT register. 1h = Temperature warning event occurred or cleared. When the TW bit is flagged to logic 1, it indicates the temperature warning event has occurred. The bit is also flagged to logic 1 when the event clears. For more details about the temperature warning operation, please refer to section Temperature Warning (TW) |
4 | TSD | RC | 0h |
0h = No temperature shutdown event occurred or the event status got cleared after a READ command was executed on the INT_STAT register. 1h = Temperature shutdown event occurred or cleared. When the TSD bit is flagged to logic 1, it indicates the temperature shutdown event has occurred. The bit is also flagged to logic 1 when the event clears. For more details about the temperature shutdown operation, please refer to section Temperature shutdown (TSD) |
3 | SSC | RC | 0h |
0h = No switch state change occurred or the status got cleared after a READ command was executed on the INT_STAT register. 1h = Switch state change occurred. The Switch State Change (SSC) bit indicates whether input threshold crossing has occurred from switch inputs IN0 to IN23. This bit is also flagged to logic 1 after the first polling cycle is completed after device polling is triggered. |
2 | PRTY_FAIL | RC | 0h |
0h = No parity error occurred in the last received SI stream or the error status got cleared after a READ command was executed on the INT_STAT register. 1h = Parity error occurred. When the PRTY_FAIL bit is flagged to logic 1, it indicates the last SPI Slave In (SI) transaction has a parity error. The device uses odd parity. If the total number of ones in the received data (including the parity bit) is an even number, the received data is discarded. The value of this register bit is mirrored to the PRTY_FLAG SPI status flag. |
1 | SPI_FAIL | RC | 0h |
0h = 32 clock pulse during a CS = low sequence was detected or the error status got cleared after a READ command was executed on the INT_STAT register. 1h = SPI error occurred When the SPI_FAIL bit is flagged to logic 1, it indicates the last SPI Slave In (SI) transaction is invalid. To program a complete word, 32 bits of information must be entered into the device. The SPI logic counts the number of bits clocked into the IC and enables data latching only if exactly 32 bits have been clocked in. In case the word length exceeds or does not meet the required length, the SPI_FAIL bit is flagged to logic 1, and the data received is considered invalid. The value of this register bit is mirrored to the SPI_FLAG SPI status flag. Note the SPI_FAIL bit is not flagged if SCLK is not present. |
0 | POR | RC | 1h |
0h = no Power-On-Reset (POR) event occurred or the status got cleared after a READ command was executed on the INT_STAT register. 1h = Power-On-Reset (POR) event occurred. The Power-On-Reset (POR) interrupt bit indicates whether a reset event has occurred. A reset event sets the registers to their default values and re-initializes the device state machine. This bit is asserted after a successful power-on-reset, hardware reset, or software reset. The value of this register bit is mirrored to the POR SPI status flag. |
CRC is shown in Figure 37 and described in Table 14.
Return to Summary Table.
This register returns the CRC-16-CCCIT calculation result. The microcontroller can compare this value with its own calculated value to ensure correct register settings are programmed to the device.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRC | ||||||||||||||||||||||
R-0h | R-FFFFh | ||||||||||||||||||||||
LEGEND: R = Read only |
IN_STAT_MISC is shown in Figure 38 and described in Table 15.
Return to Summary Table.
This register indicates current device status unrelated to switch input monitoring.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ADC_D | IN3_D | IN2_D | IN1_D | IN0_D | ||
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VS1_STAT | VS0_STAT | UV_STAT | OV_STAT | TW_STAT | TSD_STAT | ||
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||
IN_STAT_COMP is shown in Figure 39 and described in Table 16.
Return to Summary Table.
This register indicates whether an input is below or above the comparator threshold when it is configured as comparator input mode.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
INC_23 | INC_22 | INC_21 | INC_20 | INC_19 | INC_18 | INC_17 | INC_16 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INC_15 | INC_14 | INC_13 | INC_12 | INC_11 | INC_10 | INC_9 | INC_8 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INC_7 | INC_6 | INC_5 | INC_4 | INC_3 | INC_2 | INC_1 | INC_0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
LEGEND: R = Read only |
IN_STAT_ADC0 is shown in Figure 40 and described in Table 17.
Return to Summary Table.
This register indicates whether an input is below or above the programmed threshold (for IN0-IN11) when it is configured as ADC input mode. For IN12-IN17, there are 2 thresholds and the register bits indicate whether the input is below, above or in-between the 2 thresholds.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
INA_17 | INA_16 | INA_15 | INA_14 | ||||
R-0h | R-0h | R-0h | R-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INA_13 | INA_12 | INA_11 | INA_10 | INA_9 | INA_8 | ||
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INA_7 | INA_6 | INA_5 | INA_4 | INA_3 | INA_2 | INA_1 | INA_0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
LEGEND: R = Read only |
IN_STAT_ADC1 is shown in Figure 41 and described in Table 18.
Return to Summary Table.
This register indicates whether an input is above or below the programmed thresholds 3A, 3B, and 3C when it is configured as ADC input mode. For IN23, there are 5 thresholds that can be programmed.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 |
RESERVED | INA_23 | ||||||||||
R-0h | R-0h | ||||||||||
11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INA_23 | INA_22 | INA_21 | INA_20 | INA_19 | INA_18 | ||||||
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||||||
LEGEND: R = Read only |
IN_STAT_MATRIX0 is shown in Figure 42 and described in Table 19.
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This register indicates whether an input is below or above the programmed threshold in the matrix polling mode for switches connected to IN10-IN13.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
INMAT_13_IN9 | INMAT_13_IN8 | INMAT_13_IN7 | INMAT_13_IN6 | INMAT_13_IN5 | INMAT_13_IN4 | INMAT_12_IN9 | INMAT_12_IN8 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INMAT_12_IN7 | INMAT_12_IN6 | INMAT_12_IN5 | INMAT_12_IN4 | INMAT_11_IN9 | INMAT_11_IN8 | INMAT_11_IN7 | INMAT_11_IN6 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INMAT_11_IN5 | INMAT_11_IN4 | INMAT_10_IN9 | INMAT_10_IN8 | INMAT_10_IN7 | INMAT_10_IN6 | INMAT_10_IN5 | INMAT_10_IN4 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
LEGEND: R = Read only |
IN_STAT_MATRIX1 is shown in Figure 43 and described in Table 20.
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This register indicates whether an input is below or above the programmed threshold in the matrix polling mode for switches connected to IN14-IN15. This register also indicates the status of IN0-IN11 with respect to. the common threshold THRES_COM.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IN11_COM | IN10_COM | IN9_COM | IN8_COM | IN7_COM | IN6_COM | IN5_COM | IN4_COM |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
IN3_COM | IN2_COM | IN1_COM | IN0_COM | INMAT_15_IN9 | INMAT_15_IN8 | INMAT_15_IN7 | INMAT_15_IN6 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INMAT_15_IN5 | INMAT_15_IN4 | INMAT_14_IN9 | INMAT_14_IN8 | INMAT_14_IN7 | INMAT_14_IN6 | INMAT_14_IN5 | INMAT_14_IN4 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
LEGEND: R = Read only |
ANA_STAT0 is shown in Figure 44 and described in Table 21.
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23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IN1_ANA | IN0_ANA | |||||||||||||||||||||
R-0h | R-0h | R-0h | |||||||||||||||||||||
LEGEND: R = Read only |
ANA_STAT1 is shown in Figure 45 and described in Table 22.
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23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IN5_ANA | IN4_ANA | |||||||||||||||||||||
R-0h | R-0h | R-0h | |||||||||||||||||||||
LEGEND: R = Read only |
ANA_STAT2 is shown in Figure 46 and described in Table 23.
Return to Summary Table.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IN5_ANA | IN4_ANA | |||||||||||||||||||||
R-0h | R-0h | R-0h | |||||||||||||||||||||
LEGEND: R = Read only |
ANA_STAT3 is shown in Figure 47 and described in Table 24.
Return to Summary Table.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IN7_ANA | IN6_ANA | |||||||||||||||||||||
R-0h | R-0h | R-0h | |||||||||||||||||||||
LEGEND: R = Read only |
ANA_STAT4 is shown in Figure 48 and described in Table 25.
Return to Summary Table.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IN9_ANA | IN8_ANA | |||||||||||||||||||||
R-0h | R-0h | R-0h | |||||||||||||||||||||
LEGEND: R = Read only |
ANA_STAT5 is shown in Figure 49 and described in Table 26.
Return to Summary Table.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IN11_ANA | IN10_ANA | |||||||||||||||||||||
R-0h | R-0h | R-0h | |||||||||||||||||||||
LEGEND: R = Read only |
ANA_STAT6 is shown in Figure 50 and described in Table 27.
Return to Summary Table.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IN13_ANA | IN12_ANA | |||||||||||||||||||||
R-0h | R-0h | R-0h | |||||||||||||||||||||
LEGEND: R = Read only |
ANA_STAT7 is shown in Figure 51 and described in Table 28.
Return to Summary Table.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IN15_ANA | IN14_ANA | |||||||||||||||||||||
R-0h | R-0h | R-0h | |||||||||||||||||||||
LEGEND: R = Read only |
ANA_STAT8 is shown in Figure 52 and described in Table 29.
Return to Summary Table.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IN17_ANA | IN16_ANA | |||||||||||||||||||||
R-0h | R-0h | R-0h | |||||||||||||||||||||
LEGEND: R = Read only |
ANA_STAT9 is shown in Figure 53 and described in Table 30.
Return to Summary Table.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IN19_ANA | IN18_ANA | |||||||||||||||||||||
R-0h | R-0h | R-0h | |||||||||||||||||||||
LEGEND: R = Read only |
ANA_STAT10 is shown in Figure 54 and described in Table 31.
Return to Summary Table.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IN21_ANA | IN20_ANA | |||||||||||||||||||||
R-0h | R-0h | R-0h | |||||||||||||||||||||
LEGEND: R = Read only |
ANA_STAT11 is shown in Figure 55 and described in Table 32.
Return to Summary Table.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IN23_ANA | IN22_ANA | |||||||||||||||||||||
R-0h | R-0h | R-0h | |||||||||||||||||||||
LEGEND: R = Read only |
ANA_STAT12 is shown in Figure 56 and described in Table 33.
Return to Summary Table.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADC_SELF_ANA | VS_ANA | |||||||||||||||||||||
R-0h | R-0h | R-0h | |||||||||||||||||||||
LEGEND: R = Read only |
CONFIG is shown in Figure 57 and described in Table 34.
Return to Summary Table.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
VS_RATIO | ADC_DIAG_T | WET_D_IN3_EN | WET_D_IN2_EN | WET_D_IN1_EN | WET_D_IN0_EN | VS_MEAS_EN | TW_CUR_DIS_CSI |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DET_FILTER | TW_CUR_DIS_CSO | INT_CONFIG | TRIGGER | POLL_EN | CRC_T | POLL_ACT_TIME | |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POLL_ACT_TIME | POLL_TIME | RESET | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
LEGEND: R/W = Read/Write |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
23 | VS_RATIO | R/W | 0h |
0h = Use voltage divider factor of 3 for the VS measurement 1h = Use voltage divider factor of 10 for the VS measurement |
22 | ADC_DIAG_T | R/W | 0h |
For detailed descriptions for the ADC self-diagnostic feature, refer to section ADC Self-Diagnostic 0h = Disable ADC self-diagnostic feature 1h = Enable ADC self-diagnostic feature |
21 | WET_D_IN3_EN | R/W | 0h |
0h = Disable wetting current diagnostic for input IN3 1h = Enable wetting current diagnostic for input IN3 |
20 | WET_D_IN2_EN | R/W | 0h |
0h = Disable wetting current diagnostic for input IN2 1h = Enable wetting current diagnostic for input IN2 |
19 | WET_D_IN1_EN | R/W | 0h |
0h = Disable wetting current diagnostic for input IN1 1h = Enable wetting current diagnostic for input IN1 |
18 | WET_D_IN0_EN | R/W | 0h |
0h = Disable wetting current diagnostic for input IN0 1h = Enable wetting current diagnostic for input IN0 |
17 | VS_MEAS_EN | R/W | 0h |
For detailed descriptions for the VS measurement, refer to section VS Measurement. 0h = Disable VS measurement at the end of every polling cycle 1h = Enable VS measurement at the end of every polling cycle |
16 | TW_CUR_DIS_CSI | R/W | 0h |
0h = Enable wetting current reduction (to 2 mA) for 10mA and 15mA settings upon TW event for all inputs enabled with CSI. 1h = Disable wetting current reduction (to 2 mA) for 10mA and 15mA settings upon TW event for all inputs enabled with CSI. |
15-14 | DET_FILTER | R/W | 0h |
For detailed descriptions for the detection filter, refer to section Detection Filter. 0h = every sample is valid and taken for threshold evaluation 1h = 2 consecutive and equal samples required to be valid data 2h = 3 consecutive and equal samples required to be valid data 3h = 4 consecutive and equal samples required to be valid data |
13 | TW_CUR_DIS_CSO | R/W | 0h |
0h = Enable wetting current reduction (to 2mA) for 10mA and 15mA settings upon TW event for all inputs enabled with CSO. 1h = Disable wetting current reduction (to 2mA) for 10mA and 15mA settings upon TW event for all inputs enabled with CSO. |
12 | INT_CONFIG | R/W | 0h |
For detailed descriptions for the INT pin assertion scheme, refer to section Interrupt Generation and /INT Assertion. 0h = INT pin assertion scheme set to static 1h = INT pin assertion scheme set to dynamic |
11 | TRIGGER | R/W | 0h |
When the TRIGGER bit is set to logic 1, normal device operation (wetting current activation and polling) starts. To stop device operation and keep the device in an idle state, de-assert this bit to 0. After device normal operation is triggered, if at any time the device setting needs to be re-configured, the microcontroller is required to first set the bit TRIGGER to logic 0 to stop device operation. Once the re-configuration is completed, the microcontroller can set the TRIGGER bit back to logic 1 to re-start device operation. If re-configuration is done on the fly without first stopping the device operation, false switch status could be reported and accidental interrupt might be issued. The following register bits are the exception and can be configured when TRIGGER bit is set to logic 1:
0h = Stop TIC12400 from normal operation. 1h = Trigger TIC12400 normal operation |
10 | POLL_EN | R/W | 0h |
0h = Polling disabled. Device operates in continuous mode. 1h = Polling enabled and the device operates in one of the polling modes. |
9 | CRC_T | R/W | 0h |
Set this bit to 1 to trigger a CRC calculation on all the configuration register bits. Once triggered, it is strongly recommended the SPI master does not change the content of the configuration registers until the CRC calculation is completed to avoid erroneous CRC calculation result. The TIC12400 sets the CRC_CALC interrupt bit and asserts the INT pin low when the CRC calculation is completed. The calculated result will be available in the CRC register. This bit self-clears back to 0 after CRC calculation is executed. 0h = no CRC calculation triggered 1h = trigger CRC calculation |
8-5 | POLL_ACT_TIME | R/W | 0h |
0h = 64μs 1h = 128μs 2h = 192μs 3h = 256μs 4h = 320μs 5h = 384μs 6h = 448μs 7h = 512μs 8h = 640μs 9h = 768μs Ah = 896μs Bh = 1024μs Ch = 2048μs Dh-15h = 512μs (most frequently-used setting) |
4-1 | POLL_TIME | R/W | 0h |
0h = 2ms 1h = 4ms 2h = 8ms 3h = 16ms 4h = 32ms 5h = 48ms 6h = 64ms 7h = 128ms 8h = 256ms 9h = 512ms Ah = 1024ms Bh = 2048ms Ch = 4096ms Dh-15h = 8ms (most frequently-used setting) |
0 | RESET | R/W | 0h |
0h = No reset 1h = Trigger software reset of the device. |
IN_EN is shown in Figure 58 and described in Table 35.
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23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IN_EN_23 | IN_EN_22 | IN_EN_21 | IN_EN_20 | IN_EN_19 | IN_EN_18 | IN_EN_17 | IN_EN_16 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
IN_EN_15 | IN_EN_14 | IN_EN_13 | IN_EN_12 | IN_EN_11 | IN_EN_10 | IN_EN_9 | IN_EN_8 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IN_EN_7 | IN_EN_6 | IN_EN_5 | IN_EN_4 | IN_EN_3 | IN_EN_2 | IN_EN_1 | IN_EN_0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write |
CS_SELECT is shown in Figure 59 and described in Table 36.
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23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 |
RESERVED | |||||||||||
R-0h | |||||||||||
11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CS_IN9 | CS_IN8 | CS_IN7 | CS_IN6 | CS_IN5 | CS_IN4 | CS_IN3 | CS_IN2 | CS_IN1 | CS_IN0 | |
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; R = Read only |
WC_CFG0 is shown in Figure 60 and described in Table 37.
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23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 |
WC_IN11 | WC_IN10 | WC_IN8_IN9 | WC_IN6_IN7 | ||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||
11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WC_IN5 | WC_IN4 | WC_IN2_IN3 | WC_IN0_IN1 | ||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write |
WC_CFG1 is shown in Figure 61 and described in Table 38.
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23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 |
RESERVED | AUTO_SCALE_DIS_CSI | AUTO_SCALE_DIS_CSO | WC_IN23 | WC_IN22 | WC_IN20_IN21 | ||||||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||
11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WC_IN18_IN19 | WC_IN16_IN17 | WC_IN14_IN15 | WC_IN12_IN13 | ||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; R = Read only |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
24-23 | RESERVED | R | 0h |
Reserved |
22 | AUTO_SCALE_DIS_CSI | R/W | 0h |
0h = Enable wetting current auto-scaling (to 2mA) in continuous mode for 10mA and 15mA settings upon switch closure for all inputs enabled with CSI 1h = Disable wetting current auto-scaling (to 2mA) in continuous mode for 10mA and 15mA settings upon switch closure for all inputs enabled with CS For detailed descriptions for the wetting current auto-scaling, refer to section Wetting Current Auto-Scaling. |
21 | AUTO_SCALE_DIS_CSO | R/W | 0h |
0h = Enable wetting current auto-scaling (to 2mA) in continuous mode for 10mA and 15mA settings upon switch closure for all inputs enabled with CSO 1h = Disable wetting current auto-scaling (to 2mA) in continuous mode for 10mA and 15mA settings upon switch closure for all inputs enabled with CSO For detailed descriptions for the wetting current auto-scaling, refer to section Wetting Current Auto-Scaling. |
20-18 | WC_IN23 | R/W | 0h |
0h = no wetting current 1h = 1mA (typ.) wetting current 2h = 2mA (typ.) wetting current 3h = 5mA (typ.) wetting current 4h = 10mA (typ.) wetting current 5h-7h = 15mA (typ.) wetting current |
17-15 | WC_IN22 | R/W | 0h |
0h = no wetting current 1h = 1mA (typ.) wetting current 2h = 2mA (typ.) wetting current 3h = 5mA (typ.) wetting current 4h = 10mA (typ.) wetting current 5h-7h = 15mA (typ.) wetting current |
14-12 | WC_IN20_IN21 | R/W | 0h |
0h = no wetting current 1h = 1mA (typ.) wetting current 2h = 2mA (typ.) wetting current 3h = 5mA (typ.) wetting current 4h = 10mA (typ.) wetting current 5h-7h = 15mA (typ.) wetting current |
11-9 | WC_IN18_IN19 | R/W | 0h |
0h = no wetting current 1h = 1mA (typ.) wetting current 2h = 2mA (typ.) wetting current 3h = 5mA (typ.) wetting current 4h = 10mA (typ.) wetting current 5h-7h = 15mA (typ.) wetting current |
8-6 | WC_IN16_IN17 | R/W | 0h |
0h = no wetting current 1h = 1mA (typ.) wetting current 2h = 2mA (typ.) wetting current 3h = 5mA (typ.) wetting current 4h = 10mA (typ.) wetting current 5h-7h = 15mA (typ.) wetting current |
5-3 | WC_IN14_IN15 | R/W | 0h |
0h = no wetting current 1h = 1mA (typ.) wetting current 2h = 2mA (typ.) wetting current 3h = 5mA (typ.) wetting current 4h = 10mA (typ.) wetting current 5h-7h = 15mA (typ.) wetting current |
2-0 | WC_IN12_IN13 | R/W | 0h |
0h = no wetting current 1h = 1mA (typ.) wetting current 2h = 2mA (typ.) wetting current 3h = 5mA (typ.) wetting current 4h = 10mA (typ.) wetting current 5h-7h = 15mA (typ.) wetting current |
CCP_CFG0 is shown in Figure 62 and described in Table 39.
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23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 |
RESERVED | |||||||||||
R-0h | |||||||||||
11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CCP_TIME | WC_CCP3 | WC_CCP2 | WC_CCP1 | WC_CCP0 | ||||||
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
LEGEND: R/W = Read/Write; R = Read only |
CCP_CFG1 is shown in Figure 63 and described in Table 40.
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23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CCP_IN23 | CCP_IN22 | CCP_IN21 | CCP_IN20 | CCP_IN19 | CCP_IN18 | CCP_IN17 | CCP_IN16 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CCP_IN15 | CCP_IN14 | CCP_IN13 | CCP_IN12 | CCP_IN11 | CCP_IN10 | CCP_IN9 | CCP_IN8 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CCP_IN7 | CCP_IN6 | CCP_IN5 | CCP_IN4 | CCP_IN3 | CCP_IN2 | CCP_IN1 | CCP_IN0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write |
THRES_COMP is shown in Figure 64 and described in Table 41.
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23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | THRES_COMP_IN20_IN23 | THRES_COMP_IN16_IN19 | |||||
R-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
THRES_COMP_IN12_IN15 | THRES_COMP_IN8_IN11 | THRES_COMP_IN4_IN7 | THRES_COMP_IN0_IN3 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
LEGEND: R/W = Read/Write; R = Read only |
INT_EN_COMP1 is shown in Figure 65 and described in Table 42.
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23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 |
INC_EN_11 | INC_EN_10 | INC_EN_9 | INC_EN_8 | INC_EN_7 | INC_EN_6 | ||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||
11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INC_EN_5 | INC_EN_4 | INC_EN_3 | INC_EN_2 | INC_EN_1 | INC_EN_0 | ||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write |
INT_EN_COMP2 is shown in Figure 66 and described in Table 43.
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23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 |
INC_EN_23 | INC_EN_22 | INC_EN_21 | INC_EN_20 | INC_EN_19 | INC_EN_18 | ||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||
11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INC_EN_17 | INC_EN_16 | INC_EN_15 | INC_EN_14 | INC_EN_13 | INC_EN_12 | ||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write |
INT_EN_CFG0 is shown in Figure 67 and described in Table 44.
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23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ADC_DIAG_EN | WET_DIAG_EN | VS1_EN | VS0_EN | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRC_CALC_EN | UV_EN | OV_EN | TW_EN | TSD_EN | SSC_EN | PRTY_FAIL_EN | SPI_FAIL_EN |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; R = Read only |
INT_EN_CFG1 is shown in Figure 68 and described in Table 45.
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23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 |
IN11_EN | IN10_EN | IN9_EN | IN8_EN | IN7_EN | IN6_EN | ||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||
11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IN5_EN | IN4_EN | IN3_EN | IN2_EN | IN1_EN | IN0_EN | ||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write |
INT_EN_CFG2 is shown in Figure 69 and described in Table 46.
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23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 |
IN17_EN | IN16_EN | IN15_EN | |||||||||
R/W-0h | R/W-0h | R/W-0h | |||||||||
11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IN14_EN | IN13_EN | IN12_EN | |||||||||
R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write |
INT_EN_CFG3 is shown in Figure 70 and described in Table 47.
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23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 |
IN21_EN | IN20_EN | ||||||||||
R/W-0h | R/W-0h | ||||||||||
11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IN19_EN | IN18_EN | ||||||||||
R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write |
INT_EN_CFG4 is shown in Figure 71 and described in Table 48.
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23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 |
VS_TH1_EN | VS_TH0_EN | IN23_EN | |||||||||
R/W-0h | R/W-0h | R/W-0h | |||||||||
11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IN23_EN | IN22_EN | ||||||||||
R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write |
THRES_CFG0 is shown in Figure 72 and described in Table 49.
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23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | THRES1 | THRES0 | |||||||||||||||||||||
R-0h | R-0h | R-0h |
LEGEND: R/W = Read/Write; R = Read only |
THRES_CFG1 is shown in Figure 73 and described in Table 50.
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23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | THRES3 | THRES2 | |||||||||||||||||||||
R-0h | R-0h | R-0h |
LEGEND: R/W = Read/Write; R = Read only |
THRES_CFG2 is shown in Figure 74 and described in Table 51.
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23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | THRES5 | THRES4 | |||||||||||||||||||||
R-0h | R-0h | R-0h |
LEGEND: R/W = Read/Write; R = Read only |
THRES_CFG3 is shown in Figure 75 and described in Table 52.
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23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | THRES6 | THRES7 | |||||||||||||||||||||
R-0h | R-0h | R-0h |
LEGEND: R/W = Read/Write; R = Read only |
THRES_CFG4 is shown in Figure 76 and described in Table 53.
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23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | THRES9 | THRES8 | |||||||||||||||||||||
R-0h | R-0h | R-0h |
LEGEND: R/W = Read/Write; R = Read only |
THRESMAP_CFG0 is shown in Figure 77 and described in Table 54.
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23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 |
THRESMAP_IN7 | THRESMAP_IN6 | THRESMAP_IN5 | THRESMAP_IN4 | ||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||
11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
THRESMAP_IN3 | THRESMAP_IN2 | THRESMAP_IN1 | THRESMAP_IN0 | ||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write |
THRESMAP_CFG1 is shown in Figure 78 and described in Table 55.
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23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 |
RESERVED | THRESMAP_IN12_IN17_THRES2B | THRESMAP_IN12_IN17_THRES2A | |||||||||
R/W-0h | R/W-0h | R/W-0h | |||||||||
11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
THRESMAP_IN11 | THRESMAP_IN10 | THRESMAP_IN9 | THRESMAP_IN8 | ||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; R = Read only |
THRESMAP_CFG2 is shown in Figure 79 and described in Table 56.
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23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 |
RESERVED | THRESMAP_VS1_THRES2B | THRESMAP_VS1_THRES2A | THRESMAP_VS0_THRES2B | ||||||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||
11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
THRESMAP_VS0_THRES2A | THRESMAP_IN18_IN23_THRES3C | THRESMAP_IN18_IN23_THRES3B | THRESMAP_IN18_IN23_THRES3A | ||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; R = Read only |
Matrix is shown in Figure 80 and described in Table 57.
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23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 |
RESERVED | IN_COM_EN | THRES_COM | |||||||||
R-0h | R/W-0h | R/W-0h | |||||||||
11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
THRES_COM | MATRIX | POLL_ACT_TIME_M | |||||||||
R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; R = Read only |
Mode is shown in Figure 81 and described in Table 58.
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23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 |
M_IN23 | M_IN22 | M_IN21 | M_IN20 | M_IN19 | M_IN18 | M_IN17 | M_IN16 | M_IN15 | M_IN14 | M_IN13 | M_IN12 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
M_IN11 | M_IN10 | M_IN9 | M_IN8 | M_IN7 | M_IN6 | M_IN5 | M_IN4 | M_IN3 | M_IN2 | M_IN1 | M_IN0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write |
When configuring the TIC12400, it is critical to follow the programming guideline summarized below (see Table 59) to ensure proper behavior of the device.
Category | Programming requirement |
---|---|
Threshold setup:
|
|
Threshold setup:
|
|
4x4 matrix mode (MATRIX [4:3] = 2'b01) |
|
5x5 matrix mode (MATRIX [4:3] = 2'b10) |
|
6x6 Matrix Mode (MATRIX [4:3]= 2’b11) |
|
Clean Current Polling (if CCP_INx= 1 in the CCP_CFG1 register) | At least one input (standard or matrix) or the VS measurement has to be enabled: IN_EN_x= 1 in the IN_EN register or CONFIG [16]= 1’b1(1) |
Wetting current auto-scaling (if WC_CFG1 [22:21] != 2b’11) | |
Wetting current diagnostic (If CONFIG [21:18] != 4b’0000) |
|
|
tPOLL_TIME and tPOLL_ACT_TIME settings have to meet the below requirement: tPOLL_TIME ≥ 1.3 ×[ tPOLL_ACT_TIME + n × 24μs + 10 μs](3)(4)
|
Matrix polling mode | tPOLL_TIME ,tPOLL_ACT_TIME, and tPOLL_ACT_TIME_M settings have to meet the below requirement: tPOLL_TIME > 1.3 × [ m × tPOLL_ACT_TIME_M + tPOLL_ACT_TIME + n × 24μs + 10 μs] (3)(4)
|