SCPS269
September 2017
TIC12400
PRODUCTION DATA.
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
VS Pin
8.3.2
VDD Pin
8.3.3
Device Initialization
8.3.4
Device Trigger
8.3.5
Device Reset
8.3.5.1
VS Supply POR
8.3.5.2
Hardware Reset
8.3.5.3
Software Reset
8.3.6
VS Under-Voltage (UV) Condition
8.3.7
VS Over-Voltage (OV) Condition
8.3.8
Switch inputs Settings
8.3.8.1
Input Current Source/Sink Selection
8.3.8.2
Input Mode Selection
8.3.8.3
Input Enable Selection
8.3.8.4
Thresholds Adjustment
8.3.8.5
Wetting Current Configuration
8.3.9
Interrupt Generation and INT Assertion
8.3.9.1
INT Pin Assertion Scheme
8.3.9.2
Interrupt Idle Time (tINT_IDLE) Time
8.3.9.3
Microcontroller Wake-Up
8.3.9.4
Interrupt Enable/disable And Interrupt generation Conditions
8.3.9.5
Detection Filter
8.3.10
Temperature Monitor
8.3.10.1
Temperature Warning (TW)
8.3.10.2
Temperature Shutdown (TSD)
8.3.11
Parity Check And Parity Generation
8.3.12
Cyclic Redundancy Check (CRC)
8.4
Device Functional Modes
8.4.1
Continuous Mode
8.4.2
Polling Mode
8.4.2.1
Standard Polling
8.4.2.2
Matrix Polling
8.4.3
Additional Features
8.4.3.1
Clean Current Polling (CCP)
8.4.3.2
Wetting Current Auto-Scaling
8.4.3.3
VS Measurement
8.4.3.4
Wetting Current Diagnostic
8.4.3.5
ADC Self-Diagnostic
8.5
Programming
8.5.1
SPI Communication Interface Buses
8.5.1.1
Chip Select (CS)
8.5.1.2
System Clock (SCLK)
8.5.1.3
Slave In (SI)
8.5.1.4
Slave Out (SO)
8.5.2
SPI Sequence
8.5.2.1
Read Operation
8.5.2.2
Write Operation
8.5.2.3
Status Flag
8.6
Register Maps
8.6.1
DEVICE_ID register (Offset = 1h) [reset = 20h]
8.6.2
INT_STAT Register (Offset = 2h) [reset = 1h]
8.6.3
CRC Register (Offset = 3h) [reset = FFFFh]
8.6.4
IN_STAT_MISC Register (Offset = 4h) [reset = 0h]
8.6.5
IN_STAT_COMP Register (Offset = 5h) [reset = 0h]
8.6.6
IN_STAT_ADC0 Register (Offset = 6h) [reset = 0h]
8.6.7
IN_STAT_ADC1 Register (Offset = 7h) [reset = 0h]
8.6.8
IN_STAT_MATRIX0 Register (Offset = 8h) [reset = 0h]
8.6.9
IN_STAT_MATRIX1 Register (Offset = 9h) [reset = 0h]
8.6.10
ANA_STAT0 Register (Offset = Ah) [reset = 0h]
8.6.11
ANA_STAT1 Register (Offset = Bh) [reset = 0h]
8.6.12
ANA_STAT2 Register (Offset = Ch) [reset = 0h]
8.6.13
ANA_STAT3 Register (Offset = Dh) [reset = 0h]
8.6.14
ANA_STAT4 Register (Offset = Eh) [reset = 0h]
8.6.15
ANA_STAT5 Register (Offset = Fh) [reset = 0h]
8.6.16
ANA_STAT6 Register (Offset = 10h) [reset = 0h]
8.6.17
ANA_STAT7 Register (Offset = 11h) [reset = 0h]
8.6.18
ANA_STAT8 Register (Offset = 12h) [reset = 0h]
8.6.19
ANA_STAT9 Register (Offset = 13h) [reset = 0h]
8.6.20
ANA_STAT10 Register (Offset = 14h) [reset = 0h]
8.6.21
ANA_STAT11 Register (Offset = 15h) [reset = 0h]
8.6.22
ANA_STAT12 Register (Offset = 16h) [reset = 0h]
8.6.23
CONFIG Register (Offset = 1Ah) [reset = 0h]
8.6.24
IN_EN Register (Offset = 1Bh) [reset = 0h]
8.6.25
CS_SELECT Register (Offset = 1Ch) [reset = 0h]
8.6.26
WC_CFG0 Register (Offset = 1Dh) [reset = 0h]
8.6.27
WC_CFG1 Register (Offset = 1Eh) [reset = 0h]
8.6.28
CCP_CFG0 Register (Offset = 1Fh) [reset = 0h]
8.6.29
CCP_CFG1 Register (Offset = 20h) [reset = 0h]
8.6.30
THRES_COMP Register (Offset = 21h) [reset = 0h]
8.6.31
INT_EN_COMP1 Register (Offset = 22h) [reset = 0h]
8.6.32
INT_EN_COMP2 Register (Offset = 23h) [reset = 0h]
8.6.33
INT_EN_CFG0 Register (Offset = 24h) [reset = 0h]
8.6.34
INT_EN_CFG1 Register (Offset = 25h) [reset = 0h]
8.6.35
INT_EN_CFG2 Register (Offset = 26h) [reset = 0h]
8.6.36
INT_EN_CFG3 Register (Offset = 27h) [reset = 0h]
8.6.37
INT_EN_CFG4 Register (Offset = 28h) [reset = 0h]
8.6.38
THRES_CFG0 Register (Offset = 29h) [reset = 0h]
8.6.39
THRES_CFG1 Register (Offset = 2Ah) [reset = 0h]
8.6.40
THRES_CFG2 Register (Offset = 2Bh) [reset = 0h]
8.6.41
THRES_CFG3 Register (Offset = 2Ch) [reset = X]
8.6.42
THRES_CFG4 Register (Offset = 2Dh) [reset = X]
8.6.43
THRESMAP_CFG0 Register (Offset = 2Eh) [reset = 0h]
8.6.44
THRESMAP_CFG1 Register (Offset = 2Fh) [reset = 0h]
8.6.45
THRESMAP_CFG2 Register (Offset = 30h) [reset = 0h]
8.6.46
Matrix Register (Offset = 31h) [reset = 0h]
8.6.47
Mode Register (Offset = 32h) [reset = 0h]
8.7
Programming Guidelines
9
Application and Implementation
9.1
Application Information
9.2
Digital IO Switches and Analog Voltage Monitoring
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Receiving Notification of Documentation Updates
12.2
Community Resources
12.3
Trademarks
12.4
Electrostatic Discharge Caution
12.5
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DCP|38
MPDS520B
Thermal pad, mechanical data (Package|Pins)
DCP|38
PPTD170A
Orderable Information
scps269_oa
scps269_pm
7
Parameter Measurement Information
Figure 9.
SPI Timing Parameters
Figure 10.
t
REACT
Timing Parameters
Figure 11.
t
SO(DIS)
Timing Parameters