SLLSFJ1D February   2022  – March 2023 TIOL112 , TIOL1123 , TIOL1125

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings - IEC Specifications
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Wake-Up Detection
      2. 8.3.2  Current Limit Configuration
      3. 8.3.3  Current Fault Detection, Indication and Auto Recovery
      4. 8.3.4  Thermal Warning, Thermal Shutdown
      5. 8.3.5  Fault Reporting (NFAULT)
      6. 8.3.6  Transceiver Function Tables
      7. 8.3.7  The Integrated Voltage Regulator (LDO)
      8. 8.3.8  Reverse Polarity Protection
      9. 8.3.9  Integrated Surge Protection and Transient Waveform Tolerance
      10. 8.3.10 Power Up Sequence (TIOL112)
      11. 8.3.11 Undervoltage Lock-Out (UVLO)
    4. 8.4 Device Functional Modes
      1. 8.4.1 NPN Configuration (N-Switch SIO Mode)
      2. 8.4.2 PNP Configuration (P-Switch SIO Mode)
      3. 8.4.3 Push-Pull, Communication Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Maximum Junction Temperature Check
        2. 9.2.2.2 Driving Capacitive Loads
        3. 9.2.2.3 Driving Inductive Loads
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1 Wake-Up Detection

The TIOL112(x) may be operated in IO-Link mode or Standard Input / Output (SIO) mode. If the device is in SIO mode and the IO-link master node wants to initiate communication with the device node, the master drives the CQ line to the opposite of its present state, and will either sink or source the current (≥ 500 mA) for the wake-up duration (typically 80 μs) depending on the CQ logic level as per the IO-Link specification. The TIOL112(x) detects this as a wake-up condition and communicates to the local microcontroller via the WAKE pin. The IO-Link communication specification requires the device node to switch to receive mode within 500 μs after receiving the wake-up signal.

For overcurrent conditions shorter or longer than a valid wake-up pulse, the WAKE pin remains in a high- impedance (inactive) state. This is illustrated in GUID-11AF1E6E-D88F-4AF7-B776-F28122A272B4.html#SLLSEV5698.

If the driver of TIOL112(x) is disabled (EN = L), any change in CQ logic level for duration tWU1 < t < tWU2 is detected as a wake-up event and WAKE asserts low for the duration of tWUL. This is illustrated in GUID-11AF1E6E-D88F-4AF7-B776-F28122A272B4.html#GUID-E75FEC9E-2A72-4C45-A485-DBBF5BA49AC3. Please refer to Table 8-4 for the summary of the conditions for Wake-Up detection.