SLLSFJ1D February   2022  – March 2023 TIOL112 , TIOL1123 , TIOL1125

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings - IEC Specifications
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Wake-Up Detection
      2. 8.3.2  Current Limit Configuration
      3. 8.3.3  Current Fault Detection, Indication and Auto Recovery
      4. 8.3.4  Thermal Warning, Thermal Shutdown
      5. 8.3.5  Fault Reporting (NFAULT)
      6. 8.3.6  Transceiver Function Tables
      7. 8.3.7  The Integrated Voltage Regulator (LDO)
      8. 8.3.8  Reverse Polarity Protection
      9. 8.3.9  Integrated Surge Protection and Transient Waveform Tolerance
      10. 8.3.10 Power Up Sequence (TIOL112)
      11. 8.3.11 Undervoltage Lock-Out (UVLO)
    4. 8.4 Device Functional Modes
      1. 8.4.1 NPN Configuration (N-Switch SIO Mode)
      2. 8.4.2 PNP Configuration (P-Switch SIO Mode)
      3. 8.4.3 Push-Pull, Communication Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Maximum Junction Temperature Check
        2. 9.2.2.2 Driving Capacitive Loads
        3. 9.2.2.3 Driving Inductive Loads
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Switching Characteristics

Over recommended operating conditions and recommended free-air temperature range (unless otherwise noted). Typical values are at L+ = 24 V, VVCC_IN = 3.3 V, VVCC_OUT = 3.3 V and TA = 25 ℃ unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DRIVER
tPLH, tPHL Driver propagation delay See GUID-11AF1E6E-D88F-4AF7-B776-F28122A272B4.html#SLLSEV53390  
See GUID-11AF1E6E-D88F-4AF7-B776-F28122A272B4.html#SLLSEV59658  
See GUID-11AF1E6E-D88F-4AF7-B776-F28122A272B4.html#SLLSEV59748  
RL = 2 kΩ
CL = 5 nF
R(SET) = 10 kΩ		 600 1200 ns
tP(skew) Driver propagation delay skew. |tPLH - tPHL | 75 ns
tPZH, tPZL Driver enable delay 4 µs
tPHZ, tPLZ Driver disable delay 4 µs
tr, tf Driver output rise, fall time 200 700 ns
|tr – tf| Difference in rise and fall time 50 ns
tWU1 Wake-up recognition begin See GUID-11AF1E6E-D88F-4AF7-B776-F28122A272B4.html#SLLSEV5698   45 60 75 µs
tWU2 Wake-up recognition end 85 100 145 µs
tpWAKE Wake-up output delay 150 µs
tSC Current fault blanking time 175 200 µs
tpSC Current fault indication delay 280 µs
tWUL Wake output pulse duration on wake detection in EN=L mode See GUID-11AF1E6E-D88F-4AF7-B776-F28122A272B4.html#GUID-E75FEC9E-2A72-4C45-A485-DBBF5BA49AC3 175 225 285 µs
tSCEN Current fault driver re-enable wait time 15 ms
t(UVLO) CQ re-enable delay after UVLO #SLLSEV53899 V(UVLO) rising threshold crossing time to CQ enable time 10 30 50 ms
RECEIVER
tND Noise suppression time #SLLSEV51167 250 ns
tPLH, tPHL Receiver propagation delay See GUID-11AF1E6E-D88F-4AF7-B776-F28122A272B4.html#SLLSEV58712   15-pF load on RX, 150 300 ns
(1) CQ output remains Hi-Z for this time
(2) Noise suppression time is defined as the permissible duration of a receive signal above/below the detection threshold without detection taking place.