SLLSFS6A September   2024  – December 2024 TIOL221

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 ESD Ratings - IEC Specifications
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1  Wake-Up Detection
      2. 7.3.2  Current Limit Configuration
        1. 7.3.2.1 Current Limit Configuration in Pin-Mode
        2. 7.3.2.2 Current Limit Configuration in SPI mode
      3. 7.3.3  CQ Current Fault Detection, Indication and Auto Recovery
      4. 7.3.4  DO Current Fault Detection, Indication and Auto Recovery
      5. 7.3.5  CQ and DI Receivers
      6. 7.3.6  Fault Reporting
        1. 7.3.6.1 Thermal Warning, Thermal Shutdown
      7. 7.3.7  The Integrated Voltage Regulator (LDO)
      8. 7.3.8  Reverse Polarity Protection
      9. 7.3.9  Integrated Surge Protection and Transient Waveform Tolerance
      10. 7.3.10 Undervoltage Lock-Out (UVLO)
      11. 7.3.11 Interrupt Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 CQ and DO Tracking mode
    5. 7.5 SPI Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Driving Capacitive Loads
        2. 8.2.2.2 Driving Inductive Loads
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 TIOL221 Registers
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGE|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Switching Characteristics

Over recommended operating conditions and recommended free-air temperature range (unless otherwise noted). Typical values are at LP = 24 V, VVOUT = 3.3 V and TA = 25 ℃ unless otherwise specified.
PARAMETER TEST CONDITIONS TEST CONDITIONS TEST CONDITIONS MIN TYP MAX UNIT
CQ, DO DRIVER
tPLH Driver propagation delay, low-to-high transition See Test Circuit for Driver Output Measurements  
and  Driver Output Switching Waveforms  
 
RL = 2 kΩ
CL = 5 nF

Push-pull and PNP configuration 

RSET = 10 kΩ		 600 1200 ns
 tPHL Driver propagation delay, high-to-low transition See Test Circuit for Driver Output Measurements  
and  Driver Output Switching Waveforms  
 
RL = 2 kΩ
CL = 5 nF

Push-pull and NPN configuration 

RSET = 10 kΩ		 600 1200 ns
tP(skew) Driver propagation delay skew. |tPLH - tPHL | See Test Circuit for Driver Output Measurements  
See Driver Output Switching Waveforms  

RL = 2 kΩ
CL = 5 nF

Push-pull configuration

RSET = 10 kΩ		 120 ns
tPZH Driver enable delay high See Test Circuit for Driver Output Measurements  
 and 
 Driver Enable/Disable Timing Diagrams    
RL = 2 kΩ
CL = 5 nF

Push-pull and PNP configuration only
 
RSET = 10 kΩ		 4 µs
tPZL Driver enable delay low See Test Circuit for Driver Output Measurements  
 and 
 Driver Enable/Disable Timing Diagrams    
RL = 2 kΩ
CL = 5 nF
Push-pull and NPN configuration only

RSET = 10 kΩ		 4 µs
tPHZ Driver disable delay high See Test Circuit for Driver Output Measurements  
 and 
 Driver Enable/Disable Timing Diagrams    
RL = 2 kΩ
CL = 5 nF
Push-pull and PNP configuration only

RSET = 10 kΩ		 4 µs
 tPLZ Driver disable delay low See Test Circuit for Driver Output Measurements  
 and 
 Driver Enable/Disable Timing Diagrams    
RL = 2 kΩ
CL = 5 nF
Push-pull and NPN configuration only

RSET = 10 kΩ		 4 µs
tr Driver output rise time See Test Circuit for Driver Output Measurements  
and  Driver Output Switching Waveforms  
 
RL = 2 kΩ
CL = 5 nF
Push-pull and PNP configuration
RSET = 10 kΩ		 200 530 900 ns
tf Driver output  fall time See Test Circuit for Driver Output Measurements  
and  Driver Output Switching Waveforms  
 
RL = 2 kΩ
CL = 5 nF
Push-pull and NPN configuration

RSET = 10 kΩ		 200 480 900 ns
|tr – tf| Difference in rise and fall time See Test Circuit for Driver Output Measurements  
and  Driver Output Switching Waveforms  
 
RL = 2 kΩ
CL = 5 nF
Push-pull configuration only

RSET = 10 kΩ		 60 ns
tWU1 Wake-up recognition begin See Wake-up recognition timing diagram   45 60 75 µs
tWU2 Wake-up recognition end 85 100 145 µs
tpWAKE Wake-up output delay 150 µs
tWUL Wake output pulse duration on wake detection 175 225 285 µs
tSC Current fault blanking time See Wake-up recognition timing diagram  
(SPI/PIN = low and 10 kΩ <= RSETx <= 110 kΩ) OR   
  
SPI/PIN=high and CQ_BL_TIME[1:0]=00b (CQ) OR DO_BL_TIME[1:0]=00b (DO)		 0.175 0.2 ms
SPI/PIN=high and CQ_BL_TIME[1:0]=01b (CQ) OR DO_BL_TIME[1:0]=01b (DO) 0.25 0.5 ms
SPI/PIN=high and CQ_BL_TIME[1:0]=10b (CQ) OR DO_BL_TIME[1:0]=10b (DO) 5 ms

(SPI/PIN = low  and ILIM_ADJ floating) OR   
  
SPI/PIN=high and CQ_BL_TIME[1:0]=11b (CQ) OR DO_BL_TIME[1:0]=11b (DO)		 0.5 2 4 µs
tAR Auto retry  time after current fault Auto retry  time after current fault SPI/PIN = L OR SPI/PIN=H and CQ_RETRY_TIME=00b 50 ms
 SPI/PIN=H and CQ_RETRY_TIME=01b 100 ms
 SPI/PIN=H and CQ_RETRY_TIME=10b 200 ms
SPI/PIN=H and CQ_RETRY_TIME=11b 500 ms
t(UVLO) CQ and DO re-enable delay after LP UVLO (1) CQ and DO re-enable delay after UVLO (1) SPI/PIN = L OR SPI/PIN=H and T_UVLO=1b0 0.05 0.25 0.5 ms
t(UVLO) CQ and DO  re-enable delay after LP UVLO (1) CQ and DO  re-enable delay after UVLO (1) SPI/PIN = L OR SPI/PIN=H and T_UVLO=1b1 10 30 50 ms
CQ, DI RECEIVER
tPLH_CQ, tPHL_CQ CQ Receiver propagation delay See Receiver Test Circuit Diagram and Receiver Timing Diagram   CL=15 pF   SPI/PIN=L OR SPI/PIN=H and CQ_RX_FILTER=1b0 0.2 0.36 µs
SPI/PIN=H and CQ_RX_FILTER=1b1 1.15 1.6 µs
tPLH_DI, tPHL_DI DI Receiver propagation delay SPI/PIN=L OR SPI/PIN=H and DI_RX_FILTER=1b0 1 1.5 µs
SPI/PIN=H and DI_RX_FILTER=1b1 1.8 2.7 µs
SPI Timing (CS, SCK, SDI, SDO/CUR_OK2)
tINT_TOG INT pin High/low time (when toggling) COUT= 10 pF 100 µs
fSCK_BURST Maximum SPI clock frequency Burst mode 10 MHz
tSCK SCK period 100 ns
tSCKH SCK pulse-width high 50 ns
tSCKL SCK pulse-width low 50 ns
fSCK Maximum SPI clock frequency Non-burst mode 12.5 MHz
tSCK SCK period 80 ns
tSCKH SCK pulse-width high 40 ns
tSCKL SCK pulse-width low 40 ns
tCSS CS  falling edge to SCK rise time 20 ns
tCSH SCK  rise to CS rise hold time 40 ns
tDH SDI hold time 10 ns
tDS SDI setup time 25 ns
tDO SDO data propagation delay COUT= 10 pF 20 ns
tDORF SDO rise and fall time COUT= 10 pF 20 ns
tCSPW Minimum CS pulse width (idle time between SPI transactions) 10 ns
(1) CQ/DO output remains Hi-Z for this time