SLLSEV6C July   2017  – February 2021 TIOS101 , TIOS1013 , TIOS1015

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Current Limit Configuration
      2. 8.3.2  Current Fault Detection, Indication and Auto Recovery
      3. 8.3.3  Thermal Warning, Thermal Shutdown
      4. 8.3.4  Fault Reporting (NFAULT)
      5. 8.3.5  Device Function Tables
      6. 8.3.6  The Integrated Voltage Regulator (LDO)
      7. 8.3.7  Reverse Polarity Protection
      8. 8.3.8  Integrated Surge Protection and Transient Waveform Tolerance
      9. 8.3.9  Power Up Sequence
      10. 8.3.10 Undervoltage Lock-Out (UVLO)
    4. 8.4 Device Functional Modes
      1. 8.4.1 NPN Configuration (N-Switch Mode)
      2. 8.4.2 PNP Configuration (P-Switch Mode)
      3. 8.4.3 Push-Pull Mode
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Maximum Junction Temperature Check
        2. 9.2.2.2 Driving Capacitive Loads
        3. 9.2.2.3 Driving Inductive Loads
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-4A68FD30-5EC0-43C7-86DF-26B42BFA5C8B-low.svg Figure 5-1 DMW Package,10-Pin (VSON),Top View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
OUT 8 O Switch output
VCC 9 POWER Supply voltage (24 V nominal)
GND 7 POWER Device ground
EN 5 I Driver enable input signal from the local controller. Logic low sets the OUT output at Hi-Z. Weak internal pull-down.
IN 4 I Transmit data input from the local controller. No effect if EN is low. Logic high sets low-side switch. Logic low sets high-side switch. Weak internal pull-up.
VCC_IN/OUT 1 POWER 3.3-V or 5-V linear regulator output; external 3.3-V or 5-V logic supply input for option without LDO.
ILIM_ADJ 6 I Input for current limit adjustment. Connect resistor RSET between ILIM_ADJ and GND.
NFAULT 2 OPEN-DRAIN Fault indicator output signal to the microcontroller. A low level indicates either an over- current, an undervoltage in supply or an overtemperature condition. Connect this pin via pull-up resistor to VCC_IN/OUT.
NC 3, 10 — No internal connection.
Thermal Pad — — Connect to GND plane for optimal thermal and electrical performance