8.3.1 Serial Interface

The TLC5940-EP has a flexible serial interface, which can be connected to microcontrollers or digital signal processors in various ways. Only 3 pins are needed to input data into the device. The rising edge of SCLK signal shifts the data from the SIN pin to the internal register. After all data is clocked in, a high-level pulse of XLAT signal latches the serial data to the internal registers. The internal registers are level-triggered latches of XLAT signal. All data are clocked in with the MSB first. The length of serial data is 96 bit or 192 bit, depending on the programming mode. Grayscale data and dot correction data can be entered during a grayscale cycle. Although new grayscale data can be clocked in during a grayscale cycle, the XLAT signal should only latch the grayscale data at the end of the grayscale cycle. Latching in new grayscale data immediately overwrites the existing grayscale data. Figure 12 shows the timing chart. More than two TLC5940-EPs can be connected in series by connecting an SOUT pin from one device to the SIN pin of the next device. An example of cascading two TLC5940-EPs is shown in Figure 13 and the timing chart is shown in Figure 14. The SOUT pin can also be connected to the controller to receive status information from TLC5940-EP as shown in Figure 23.

Figure 12. Serial Data Input Timing Chart

Figure 13. Cascading Two TLC5940-EP Devices

Figure 14. Timing Chart for Two Cascaded TLC5940-EP Devices

8.3.2 Error Information Output

The open-drain output XERR is used to report both of the TLC5940-EP error flags, TEF and LOD. During normal operating conditions, the internal transistor connected to the XERR pin is turned off. The voltage on XERR is pulled up to V_CC through an external pullup resistor. If TEF or LOD is detected, the internal transistor is turned on, and XERR is pulled to GND. Since XERR is an open-drain output, multiple ICs can be OR'ed together and pulled up to V_CC with a single pullup resistor. This reduces the number of signals needed to report a system error (see Figure 23).

To differentiate LOD and TEF signal from XERR pin, LOD can be masked out with BLANK = HIGH.

8.3.3 TEF: Thermal Error Flag

The TLC5940-EP provides a temperature error flag (TEF) circuit to indicate an overtemperature condition of the IC. If the junction temperature exceeds the threshold temperature (160°C typical), TEF becomes H and XERR pin goes to low level. When the junction temperature becomes lower than the threshold temperature, TEF becomes L and XERR pin becomes high impedance. TEF status can also be read out from the TLC5940-EP status register.

8.3.4 LOD: LED Open Detection

The TLC5940-EP has an LED-open detector that detects broken or disconnected LEDs. The LED open detector pulls the XERR pin to GND when an open LED is detected. XERR and the corresponding error bit in the Status Information Data is only active under the following open-LED conditions.

1. OUTn is on and the time tpd2 (1 µs typical) has passed.
2. The voltage of OUTn is < 0.3 V (typical)

The LOD status of each output can be also read out from the SOUT pin. See Status Information Output for details. The LOD error bits are latched into the Status Information Data when XLAT returns to a low after a high. Therefore, the XLAT pin must be pulsed high then low while XERR is active in order to latch the LOD error into the Status Information Data for subsequent reading via the serial shift register.

8.3.5 Delay Between Outputs

The TLC5940-EP has graduated delay circuits between outputs. These circuits can be found in the constant current driver block of the device (see Functional Block Diagram). The fixed-delay time is 20 ns (typical), OUT0 has no delay, OUT1 has 20-ns delay, and OUT2 has 40-ns delay, and so forth. The maximum delay is 300 ns from OUT0 to OUT15. The delay works during switch on and switch off of each output channel. These delays prevent large inrush currents which reduces the bypass capacitors when the outputs turn on.

8.3.6 Output Enable

All OUTn channels of the TLC5940-EP can be switched off with one signal. When BLANK is set high, all OUTn channels are disabled, regardless of logic operations of the device. The grayscale counter is also reset. When BLANK is set low, all OUTn channels work under normal conditions. If BLANK goes low and then back high again in less than 300 ns, all outputs programmed to turn on still turn on for either the programmed number of grayscale clocks, or the length of time that the BLANK signal was low, which ever is lower. For example, if all outputs are programmed to turn on for 1 ms, but the BLANK signal is only low for 200 ns, all outputs still turn on for 200 ns, even though some outputs are turning on after the BLANK signal has already gone high.

8.3.7 Setting Maximum Channel Current

The maximum output current per channel is programmed by a single resistor, R_(IREF), which is placed between IREF pin and GND pin. The voltage on IREF is set by an internal band gap V_(IREF) with a typical value of
1.24 V. The maximum channel current is equivalent to the current flowing through R_(IREF) multiplied by a factor of 31.5. The maximum output current per channel can be calculated by Equation 6:

Equation 6.

where

• V_(IREF) = 1.24 V.
• R_(IREF) = User-selected external resistor.

I_max must be set between 5 mA and 120 mA. The output current may be unstable if I_max is set lower than 5 mA. Output currents lower than 5 mA can be achieved by setting I_max to 5 mA or higher and then using dot correction.

Figure 1 shows the maximum output current I_O versus R_(IREF). R_(IREF) is the value of the resistor between IREF terminal to GND, and I_O is the constant output current of OUT0 to OUT15. A variable power supply may be connected to the IREF pin through a resistor to change the maximum output current per channel. The maximum output current per channel is 31.5 times the current flowing out of the IREF pin.

8.4.1 Operating Modes

The TLC5940-EP has operating modes depending on the signals DCPRG and VPRG. Table 3 shows the available operating modes. The TPS5940 GS operating mode (see Figure 12) and shift register values are not defined after power up. One solution to solve this is to set dot correction data after TLS5940 power up and switch back to GS PWM mode. The other solution is to overflow the input shift register with 193 bits of dummy data and latch it while TLS540 is in GS PWM mode. The values in the input shift register, DC register and GS register are unknown just after power on. The DC and GS register values should be properly stored through the serial interface before starting the operation.

8.4.2 Setting Dot Correction

The TLC5940-EP has the capability to fine adjust the output current of each channel OUT0 to OUT15 independently. This is also called dot correction. This feature is used to adjust the brightness deviations of LEDs connected to the output channels OUT0 to OUT15. Each of the 16 channels can be programmed with a 6-bit word. The channel output can be adjusted in 64 steps from 0% to 100% of the maximum output current I_max. Dot correction for all channels must be entered at the same time. Equation 7 determines the output current for each output n:

Equation 7.

where

• I_max = the maximum programmable output current for each output.
• DCn = the programmed dot correction value for output n (DCn = 0 to 63).
• n = 0 to 15

Figure 15 shows the dot correction data packet format which consists of 6 bits × 16 channel, total 96 bits. The format is Big-Endian format. This means that the MSB is transmitted first, followed by the MSB-1, and so forth. The DC 15.5 in Figure 15 stands for the 5^th most significant bit for output 15.

Figure 15. Dot Correction Data Packet Format

When VPRG is set to VCC, the TLC5940-EP enters the dot correction data input mode. The length of input shift register becomes 96 bits. After all serial data are shifted in, the TLC5940-EP writes the data in the input shift register to DC register when XLAT is high, and holds the data in the DC register when XLAT is low. The DC register is a level triggered latch of XLAT signal. Since XLAT is a level-triggered signal, SCLK and SIN must not be changed while XLAT is high. After XLAT goes low, data in the DC register is latched and does not change. BLANK signal does not need to be high to latch in new data. XLAT has setup time (tsu1) and hold time (th1) to SCLK as shown in Figure 16.

Figure 16. Dot Correction Data Input Timing Chart

The TLC5940-EP also has an EEPROM to store dot correction data. To store data from the dot correction register to EEPROM, DCPRG is set to high after applying V_PRG to the VPRG pin. Figure 17 shows the EEPROM programming timings. The EEPROM has a default value of all 1s.

Figure 17. EEPROM Programming Timing Chart

Figure 18. DCPRG and OUTn Timing Diagram

8.4.3 Setting Grayscale

The TLC5940-EP can adjust the brightness of each channel OUTn using a PWM control scheme. The use of 12 bits per channel results in 4096 different brightness steps, respective 0% to 100% brightness. Equation 8 determines the brightness level for each output n:

Equation 8.

where

• GSn = the programmed grayscale value for output n (GSn = 0 to 4095)
• n = 0 to 15
• Grayscale data for all OUTn

Figure 19 shows the grayscale data packet format which consists of 12 bits × 16 channels, totaling 192 bits. The format is Big-Endian format. This means that the MSB is transmitted first, followed by the MSB-1, and so forth.

Figure 19. Grayscale Data Packet Format

When VPRG is set to GND, the TLC5940-EP enters the grayscale data input mode. The device switches the input shift register to 192-bit width. After all data is clocked in, a rising edge of the XLAT signal latches the data into the grayscale register (see Figure 12). New grayscale data immediately becomes valid at the rising edge of the XLAT signal; therefore, new grayscale data should be latched at the end of a grayscale cycle when BLANK is high. The first GS data input cycle after dot correction requires an additional SCLK pulse after the XLAT signal to complete the grayscale update cycle. All GS data in the input shift register is replaced with status information data (SID) after updated the grayscale register.

8.4.4 Status Information Output

The TLC5940-EP does have a status information register, which can be accessed in grayscale mode (VPRG=GND). After the XLAT signal latches the data into the GS register the input shift register data will be replaced with status information data (SID) of the device (see Figure 19). LOD, TEF, and dot correction EEPROM data (DCPRG=LOW) or dot correction register data (DCPRG=HIGH) can be read out at SOUT pin. The status information data packet is 192 bits wide. Bits 0-15 contain the LOD status of each channel. Bit 16 contains the TEF status. If DCPRG is low, bits 24-119 contain the data of the dot-correction EEPROM. If DCPRG is high, bits 24-119 contain the data of the dot-correction register. The remaining bits are reserved. The complete status information data packet is shown in Figure 20.

SOUT outputs the MSB of the SID at the same time the SID are stored in the SID register, as shown Figure 21. The next SCLK pulse, which will be the clock for receiving the SMB of the next grayscale data, transmits MSB-1 of SID. If output voltage is < 0.3 V (typical) when the output sink current turns on, LOD status flag becomes active. The LOD status flag is an internal signal that pulls XERR pin down to low when the LOD status flag becomes active. The delay time, tpd2 (1 µs maximum), is from the time of turning on the output sink current to the time LOD status flag becomes valid. The timing for each channel's LOD status to become valid is shifted by the 30-ns (maximum) channel-to-channel turnon time. After the first GSCLK goes high, OUT0 LOD status is valid; tpd3 + tpd2 = 60 ns + 1 µs. OUT1 LOD status is valid; tpd3 + td + tpd2 = 60 ns + 30 ns + 1 µs = 1.09 µs. OUT2 LOD status is valid; tpd3 + 2*td + tpd2 = 1.12 µs, and so on. It takes 1.51 µs maximum (tpd3 + 15*td + tpd2) from the first GSCLK rising edge until all LOD become valid; tsuLOD must be > 1.51 µs (see Figure 21) to ensure that all LOD data are valid.

Figure 20. Status Information Data Packet Format

Figure 21. Readout Status Information Data (SID) Timing Chart

8.4.5 Grayscale PWM Operation

The grayscale PWM cycle starts with the falling edge of BLANK. The first GSCLK pulse after BLANK goes low increases the grayscale counter by one and switches on all OUTn with grayscale value not zero. Each following rising edge of GSCLK increases the grayscale counter by one. The TLC5940-EP compares the grayscale value of each output OUTn with the grayscale counter value. All OUTn with grayscale values equal to the counter values are switched off. A BLANK=H signal after 4096 GSCLK pulses resets the grayscale counter to zero and completes the grayscale PWM cycle (see Figure 22). When the counter reaches a count of FFFh, the counter stops counting and all outputs turn off. Pulling BLANK high before the counter reaches FFFh immediately resets the counter to zero.

Figure 22. Grayscale PWM Cycle Timing Chart