SBVS222C
February 2013 – October 2016
TLC59731
PRODUCTION DATA.
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics
6.7
Typical Characteristics
7
Parameter Measurement Information
7.1
Pin-Equivalent Input and Output Schematic Diagrams
7.2
Test Circuits
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Sink Current Value Setting
8.3.2
Resistor and Capacitor Value Setting for Shunt Regulator
8.3.3
Grayscale (GS) Control
8.3.4
EasySet and Shunt Regulator
8.3.5
No Limit Cascading
8.3.6
Connector Design
8.4
Device Functional Modes
8.4.1
Grayscale (GS) Function (PWM Control)
8.4.1.1
PWM Control
8.5
Programming
8.5.1
One-Wire Interface (EasySet) Data Writing Method
8.5.1.1
Data Transfer Rate (TCYCLE) Measurement Sequence
8.5.1.2
Data 0 and Data 1 Write Sequence (Data Write Sequence)
8.5.1.3
One Communication Cycle End of Sequence (EOS)
8.5.1.4
GS Data Latch (GSLAT) Sequence
8.5.1.5
How to Control Devices Connected in Series
8.6
Register Maps
8.6.1
Register and Data Latch Configuration
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Define Basic Parameters
9.2.2.2
Grayscale (GS) Data
9.2.3
Application Curve
9.3
System Examples
9.4
Do's and Don'ts
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Receiving Notification of Documentation Updates
12.2
Community Resources
12.3
Trademarks
12.4
Electrostatic Discharge Caution
12.5
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
D|8
MSOI002K
Thermal pad, mechanical data (Package|Pins)
Orderable Information
sbvs222c_oa
sbvs222c_pm
7 Parameter Measurement Information
7.1 Pin-Equivalent Input and Output Schematic Diagrams
Figure 5. SDI
Figure 6. SDO
1. n = 0 to 2.
Figure 7. OUT0 Through OUT2
7.2 Test Circuits
1. n = 0 to 2.
2. C
L
includes measurement probe and jig capacitance.
Figure 8. Rise Time and Fall Time Test Circuit for Out
n
1. C
L
includes measurement probe and jig capacitance.
Figure 9. Rise Time and Fall Time Test Circuit for SDO