SLLSEB8C August   2012  – April  2016 TLK105 , TLK106

PRODUCTION DATA.  

  1. 1  Introduction
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Device Overview
      1. 1.3.1 Electrostatic Discharge Caution
  2. 2 Pin Descriptions
    1. 2.1 Pin Layout
    2. 2.2 Serial Management Interface (SMI)
    3. 2.3 MAC Data Interface
    4. 2.4 10Mbs and 100Mbs PMD Interface
    5. 2.5 Clock Interface
    6. 2.6 LED Interface
    7. 2.7 Reset and Power Down
    8. 2.8 Power and Bias Connections
  3. 3 Hardware Configuration
    1. 3.1  Bootstrap Configuration
    2. 3.2  Power Supply Configuration
      1. 3.2.1 Single Supply Operation
      2. 3.2.2 Dual Supply Operation
      3. 3.2.3 Variable IO Voltage
    3. 3.3  IO Pins Hi-Z State During Reset
    4. 3.4  Auto-Negotiation
    5. 3.5  Auto-MDIX
    6. 3.6  MII Isolate Mode
    7. 3.7  PHY Address
    8. 3.8  LED Interface
    9. 3.9  Loopback Functionality
      1. 3.9.1 Near-End Loopback
      2. 3.9.2 Far-End Loopback
    10. 3.10 BIST
    11. 3.11 Cable Diagnostics
      1. 3.11.1 TDR
      2. 3.11.2 ALCD
  4. 4 Interfaces
    1. 4.1 Media Independent Interface (MII)
    2. 4.2 Reduced Media Independent Interface (RMII)
    3. 4.3 Serial Management Interface
      1. 4.3.1 Extended Address Space Access
        1. 4.3.1.1 Write Address Operation
        2. 4.3.1.2 Read Address Operation
        3. 4.3.1.3 Write (no post increment) Operation
        4. 4.3.1.4 Read (no post increment) Operation
        5. 4.3.1.5 Write (post increment) Operation
        6. 4.3.1.6 Read (post increment) Operation
  5. 5 Architecture
    1. 5.1 100Base-TX Transmit Path
      1. 5.1.1 MII Transmit Error Code Forwarding
      2. 5.1.2 4-Bit to 5-Bit Encoding
      3. 5.1.3 Scrambler
      4. 5.1.4 NRZI and MLT-3 Encoding
      5. 5.1.5 Digital to Analog Converter
    2. 5.2 100Base-TX Receive Path
      1. 5.2.1  Analog Front End
      2. 5.2.2  Adaptive Equalizer
      3. 5.2.3  Baseline Wander Correction
      4. 5.2.4  NRZI and MLT-3 Decoding
      5. 5.2.5  Descrambler
      6. 5.2.6  5B/4B Decoder and Nibble Alignment
      7. 5.2.7  Timing Loop and Clock Recovery
      8. 5.2.8  Phase-Locked Loops (PLL)
      9. 5.2.9  Link Monitor
      10. 5.2.10 Signal Detect
      11. 5.2.11 Bad SSD Detection
    3. 5.3 10Base-T Receive Path
      1. 5.3.1 10M Receive Input and Squelch
      2. 5.3.2 Collision Detection
      3. 5.3.3 Carrier Sense
      4. 5.3.4 Jabber Function
      5. 5.3.5 Automatic Link Polarity Detection and Correction
      6. 5.3.6 10Base-T Transmit and Receive Filtering
      7. 5.3.7 10Base-T Operational Modes
    4. 5.4 Auto Negotiation
      1. 5.4.1 Operation
      2. 5.4.2 Initialization and Restart
      3. 5.4.3 Next Page Support
    5. 5.5 Link Down Functionality
  6. 6 Reset and Power Down Operation
    1. 6.1 Hardware Reset
    2. 6.2 Software Reset
    3. 6.3 Power Down/Interrupt
      1. 6.3.1 Power Down Control Mode
      2. 6.3.2 Interrupt Mechanisms
    4. 6.4 Power Save Modes
  7. 7 Design Guidelines
    1. 7.1 TPI Network Circuit
    2. 7.2 Clock In (XI) Requirements
      1. 7.2.1 Oscillator
      2. 7.2.2 Crystal
    3. 7.3 Thermal Vias Recommendation
  8. 8 Register Block
    1. 8.1 Register Definition
      1. 8.1.1  Basic Mode Control Register (BMCR)
      2. 8.1.2  Basic Mode Status Register (BMSR)
      3. 8.1.3  PHY Identifier Register 1 (PHYIDR1)
      4. 8.1.4  PHY Identifier Register 2 (PHYIDR2)
      5. 8.1.5  Auto-Negotiation Advertisement Register (ANAR)
      6. 8.1.6  Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
      7. 8.1.7  Auto-Negotiate Expansion Register (ANER)
      8. 8.1.8  Auto-Negotiate Next Page Transmit Register (ANNPTR)
      9. 8.1.9  Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
      10. 8.1.10 Control register 1 (CR1)
      11. 8.1.11 Control register 2 (CR2)
      12. 8.1.12 Control Register 3 (CR3)
      13. 8.1.13 Extended Register Addressing
        1. 8.1.13.1 Register Control Register (REGCR)
        2. 8.1.13.2 Address or Data Register (ADDAR)
      14. 8.1.14 PHY Status Register (PHYSTS)
      15. 8.1.15 PHY Specific Control Register (PHYSCR)
      16. 8.1.16 MII Interrupt Status Register 1 (MISR1)
      17. 8.1.17 MII Interrupt Status Register 2 (MISR2)
      18. 8.1.18 False Carrier Sense Counter Register (FCSCR)
      19. 8.1.19 Receiver Error Counter Register (RECR)
      20. 8.1.20 BIST Control Register (BISCR)
      21. 8.1.21 RMII Control and Status Register (RCSR)
      22. 8.1.22 LED Control Register (LEDCR)
      23. 8.1.23 PHY Control Register (PHYCR)
      24. 8.1.24 10Base-T Status/Control Register (10BTSCR)
      25. 8.1.25 BIST Control and Status Register 1 (BICSR1)
      26. 8.1.26 BIST Control and Status Register2 (BICSR2)
    2. 8.2 Cable Diagnostic Control Register (CDCR)
    3. 8.3 PHY Reset Control Register (PHYRCR)
    4. 8.4 Compliance Test register (COMPTR)
    5. 8.5 TX_CLK Phase Shift Register (TXCPSR)
    6. 8.6 Power Back Off Control Register (PWRBOCR)
    7. 8.7 Voltage Regulator Control Register (VRCR)
    8. 8.8 Cable Diagnostic Configuration/Result Registers
      1. 8.8.1  ALCD Control and Results 1 (ALCDRR1)
      2. 8.8.2  Cable Diagnostic Specific Control Registers (CDSCR1 - CDSCR4)
      3. 8.8.3  Cable Diagnostic Location Results Register 1 (CDLRR1)
      4. 8.8.4  Cable Diagnostic Location Results Register 2 (CDLRR2)
      5. 8.8.5  Cable Diagnostic Location Results Register 3 (DDLRR3)
      6. 8.8.6  Cable Diagnostic Location Results Register 4 (CDLRR4)
      7. 8.8.7  Cable Diagnostic Location Results Register 5 (CDLRR5)
      8. 8.8.8  Cable Diagnostic Amplitude Results Register 1 (CDARR1)
      9. 8.8.9  Cable Diagnostic Amplitude Results Register 2 (CDARR2)
      10. 8.8.10 Cable Diagnostic Amplitude Results Register 3 (CDARR3)
      11. 8.8.11 Cable Diagnostic Amplitude Results Register 4 (CDARR4)
      12. 8.8.12 Cable Diagnostic Amplitude Results Register 5 (CDARR5)
      13. 8.8.13 Cable Diagnostic General Results Register (CDGRR)
      14. 8.8.14 ALCD Control and Results 2 (ALCDRR2)
  9. 9 Electrical Specifications
    1. 9.1 Absolute Maximum Ratings
    2. 9.2 ESD Ratings
    3. 9.3 Recommended Operating Conditions
    4. 9.4 145
      1. 9.4.1 TLK105 32-Pin Industrial Device (85°C) Thermal Characteristics
    5. 9.5 TLK106 32-Pin Extended Temperature (105°C) Device Thermal Characteristics
    6. 9.6 DC Characteristics, VDD_IO
    7. 9.7 DC Characteristics
    8. 9.8 Power Supply Characteristics
      1. 9.8.1 Active Power, Single Supply Operation
      2. 9.8.2 Active Power, Dual Supply Operation
      3. 9.8.3 Power-Down Power
    9. 9.9 AC Specifications
      1. 9.9.1  Power Up Timing
      2. 9.9.2  Reset Timing
      3. 9.9.3  MII Serial Management Timing
      4. 9.9.4  100Mb/s MII Transmit Timing
      5. 9.9.5  100Mb/s MII Receive Timing
      6. 9.9.6  100Base-TX Transmit Packet Latency Timing
      7. 9.9.7  100Base-TX Transmit Packet Deassertion Timing
      8. 9.9.8  100Base-TX Transmit Timing (tR/F and Jitter)
      9. 9.9.9  100Base-TX Receive Packet Latency Timing
      10. 9.9.10 100Base-TX Receive Packet Deassertion Timing
      11. 9.9.11 10Mbs MII Transmit Timing
      12. 9.9.12 10Mb/s MII Receive Timing
      13. 9.9.13 10Base-T Transmit Timing (Start of Packet)
      14. 9.9.14 10Base-T Transmit Timing (End of Packet)
      15. 9.9.15 10Base-T Receive Timing (Start of Packet)
      16. 9.9.16 10Base-T Receive Timing (End of Packet)
      17. 9.9.17 10Mb/s Jabber Timing
      18. 9.9.18 10Base-T Normal Link Pulse Timing
      19. 9.9.19 Auto-Negotiation Fast Link Pulse (FLP) Timing
      20. 9.9.20 100Base-TX Signal Detect Timing
      21. 9.9.21 100Mbs Loopback Timing
      22. 9.9.22 10Mbs Internal Loopback Timing
      23. 9.9.23 RMII Transmit Timing
      24. 9.9.24 RMII Receive Timing
      25. 9.9.25 Isolation Timing
  10. 10Revision History

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHB|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Electrical Specifications

All parameters are derived by test, statistical analysis, or design.

9.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
VDD_IO, AVDD33 Supply voltage –0.3 3.8 V
PFBIN1, PFBIN2 –0.3 1.8
XI DC Input voltage –0.3 3.8 V
TD-, TD+, RD-, RD+ –0.3 6
Other Inputs –0.3 3.8
XO DC Output voltage –0.3 3.8 V
Other outputs –0.3 3.8
TJ Maximum die temperature 125 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

9.2 ESD Ratings

VALUE UNIT
VESD Electrostatic discharge (ESD) performance: Human Body Model (HBM), per ANSI/ESDA/JEDEC JS001(1) All pins(3) ±4000 V
Ethernet network pins (TD+, TD–, RD+, RD–)(5) ±16000
Charged Device Model (CDM),
per JESD22-C101(2)		 All pins(4) ±750 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) Tested in accordance to JEDEC Standard 22, Test Method A114.
(4) Tested in accordance to JEDEC Standard 22, Test Method C101.
(5) Test method based upon JEDEC Standard 22 Test Method A114, Ethernet network pins (TD+, TD–, RD+, RD–) pins stressed with respect to GND.

9.3 Recommended Operating Conditions

MIN NOM MAX UNIT
DUAL SUPPLY OPERATION
Core Supply voltage (PFBIN1, PFBIN2) 1.48 1.55 1.68 V
PD Power dissipation(2) 200 mW
SINGLE SUPPLY OPERATION
(PFBOUT connected to PFBIN1, PFBIN2 See Figure 3-1)
PD Power dissipation(1) 270 mW
AVDD33 Analog 3.3-V Supply 3.0 3.3 3.6 V
VDD_IO 3.3-V Option 3.0 3.3 3.6 V
2.5-V Option 2.25 2.5 2.75
1.8-V Option (MII Mode only) 1.62 1.8 1.98
TA Ambient temperature(3) TLK105 –40 85 °C
TLK106 –40 105
(1) For 100Base-TX, When internal 1.55 V is used. Device is operated from single 3.3-V supply only.
(2) For 100Base-TX
(3) Provided that DOWN_PAD, pin 33, is soldered down. See Thermal Vias Recommendation for more detail.

9.4

9.4.1 TLK105 32-Pin Industrial Device (85°C) Thermal Characteristics

over operating free-air temperature range (unless otherwise noted)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
over operating free-air temperature range (unless otherwise noted)
THERMAL METRIC(1) TLK105L, TLK106L UNIT
RHB (VQFN)
32 PINS
RθJA Junction-to-ambient thermal resistance 36.4 °C/W
RθJB Junction-to-board thermal resistance 9.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 26.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

9.5 TLK106 32-Pin Extended Temperature (105°C) Device Thermal Characteristics

over operating free-air temperature range (unless otherwise noted)
THERMAL METRIC(1) TLK105L, TLK106L UNIT
RHB (VQFN)
32 PINS
RθJA Junction-to-ambient thermal resistance (no airflow), JEDEC high-K model 36.4 °C/W
RθJB Junction-to-board thermal resistance 9.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 26.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

9.6 DC Characteristics, VDD_IO

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
3.3V VDD_IO
VIH Input high voltage Nominal VCC = 3.3V VDD_IO = 3.3 V ±10% 2.0 V
VIL Input low voltage VDD_IO = 3.3 V±10% 0.8 V
VOL Output low voltage IOL = 4 mA VDD_IO = 3.3 V±10% 0.4 V
VOH Output high voltage IOH = –4 mA VDD_IO = 3.3 V±10% VDD_IO – 0.5 V
2.5V VDD_IO
VIH Input high voltage VDD_IO = 2.5 V±10% 1.5 V
VIL Input low voltage VDD_IO = 2.5 V±10% 0.5 V
VOL Output low voltage IOL = 2 mA VDD_IO = 2.5 V±10% 0.4 V
VOH Output high voltage IOH = –2 mA VDD_IO = 2.5 V±10% VDD_IO – 0.4 V
1.8V VDD_IO
VIH Input high voltage VDD_IO = 1.8 V±10% 1.3 V
VIL Input low voltage VDD_IO = 1.8 V±10% 0.45 V
VOL Output low voltage IOL = 2 mA VDD_IO = 1.8 V±10% 0.4 V
VOH Output high voltage IOH = –2 mA VDD_IO = 1.8 V±10% VDD_IO – 0.4 V

9.7 DC Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IIH Input high current VIN = VCC 10 μA
IIL Input low current VIN = GND 10 μA
IOZ 3-State leakage VOUT = VCC, VOUT = GND ±10 μA
RPULLUP Integrated Pullup Resistance 14.7 23.7 49.7 kΩ
RPULLDOWN Integrated Pulldown Resistance 14.5 24.9 48.1 kΩ
VTPTD_100 100M transmit voltage 0.95 1 1.05 V
VTPTDsym 100M transmit voltage symmetry ±2%
VTPTD_10 10M transmit voltage 2.2 2.5 2.8 V
CIN1 CMOS input capacitance 5 pF
COUT1 CMOS output capacitance 5 pF
VTH1 10Base-T Receive threshold 200 mV

9.8 Power Supply Characteristics

The data was measured using a TLK10x evaluation board. The current from each of the power supplies is measured and the power dissipation is computed. For the single 3.3-V external supply case the power dissipation across the internal linear regulator is also included. All the power dissipation numbers are measured at the nominal power supply and typical temperature of 25°C. The power needed is given both for the device only, and including the center tap of the transformer for a total system power requirement. The center tap of the transformer is normally connected to the 3.3-V supply, thus the current needed may also be easily calculated.

9.8.1 Active Power, Single Supply Operation

PARAMETER TEST CONDITIONS FROM POWER PINS FROM TRANSFORMER
CENTER TAP		 UNIT
100Base-TX /W Traffic (full packet 1518B rate) Single 3.3-V external supply 203 73 mW
10Base-T /W Traffic (full packet 1518B rate) 96 211

9.8.2 Active Power, Dual Supply Operation

PARAMETER TEST CONDITIONS FROM 3.3-V POWER FROM 1.55 V
PFBIN1, PFBIN2		 FROM TRANSFORMER
CENTER TAP		 UNIT
100Base-TX /W Traffic (full packet 1518B rate) Dual external supplies,
3.3 V and 1.55 V		 53 73 73 mW
10Base-T /W Traffic (full packet 1518B rate) 23 35 212

9.8.3 Power-Down Power

PARAMETER TEST CONDITIONS(1) FROM 3.3-V POWER FROM 1.55 V
PFBIN1, PFBIN2		 FROM TRANSFORMER CENTER TAP UNIT
IEEE PWDN Single 3.3-V external supply 12 – 5 mW
Passive Sleep Mode 71 – 5
Active Sleep Mode 71 – 5
IEEE PWDN Dual external supplies,
3.3 V and 1.55 V		 12 0 5
Passive Sleep Mode 21 23 5
Active Sleep Mode 21 23 5
(1) Measured under typical conditions.

9.9 AC Specifications

9.9.1 Power Up Timing

Table 9-1 Power Up Timing

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t1 Time from powerup to hardware-configuration pin transition to output-driver function, using internal POR (RESET pin tied high) 100 270 ms
t2 XI Clock initialization XI Clock must be stable for minimum of 1µs prior to configuration. 1 µs
TLK105 TLK106 td_reset_lls901_update.gif Figure 9-1 Power Up Timing

NOTE

It is important to choose pullup and-or pulldown resistors for each of the hardware configuration pins that provide fast RC time constants in order to latch in the proper value prior to the pin transitioning to an output driver.

9.9.2 Reset Timing

Table 9-2 Reset Timing

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t1 RESET pulse width XI Clock must be stable for minimum of 1µs during RESET pulse low time. 1 µs
TLK105 TLK106 td_reset_pulse_width_lls901.gif Figure 9-2 Reset Timing

9.9.3 MII Serial Management Timing

Table 9-3 MII Serial Management Timing

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t1 MDC Frequency 2.5 25 MHz
t2 MDC to MDIO (Output) Delay Time 0 30 ns
t3 MDIO (Input) to MDC Hold Time 10 ns
t4 MDIO (Input) to MDC Setup Time 10 ns
TLK105 TLK106 t0340-01_lls931.gif Figure 9-3 MII Serial Management Timing

9.9.4 100Mb/s MII Transmit Timing

Table 9-4 100Mb/s MII Transmit Timing

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t1 TX_CLK High Time 100Mbs Normal mode 16 20 24 ns
t2 TX_CLK Low Time
t3 TXD[3:0], TX_EN Data Setup to TX_CLK 100Mbs Normal mode 10 ns
t4 TXD[3:0], TX_EN Data Hold from TX_CLK 100Mbs Normal mode 0 ns
TLK105 TLK106 t0341-01_lls931.gif Figure 9-4 100Mb/s MII Transmit Timing

9.9.5 100Mb/s MII Receive Timing

Table 9-5 100Mb/s MII Receive Timing

PARAMETER(1) TEST CONDITIONS MIN TYP MAX UNIT
t1 RX_CLK High Time 100Mbs Normal mode 16 20 24 ns
t2 RX_CLK Low Time
t3 RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 100Mbs Normal mode 10 30 ns
(1) RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated.
TLK105 TLK106 t0342-01_lls931.gif Figure 9-5 100Mb/s MII Receive Timing

9.9.6 100Base-TX Transmit Packet Latency Timing

Table 9-6 100Base-TX Transmit Packet Latency Timing

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t1 TX_CLK to PMD Output Pair Latency 100Mbs Normal mode(1) 4.8 bits(2)
(1) For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN to the first bit of the 'J' code group as output from the PMD Output Pair. 1 bit time = 10ns in 100Mbs mode.
(2) 1 bit time is equal 10 nS in 100 Mb/s mode.
TLK105 TLK106 t0343-01_lls931.gif Figure 9-6 100Base-TX Transmit Packet Latency Timing

9.9.7 100Base-TX Transmit Packet Deassertion Timing

Table 9-7 100Base-TX Transmit Packet Deassertion Timing

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t1 TX_CLK to PMD Output Pair deassertion 100Mbs Normal mode 4.6 bits
TLK105 TLK106 t0344-01_lls931.gif Figure 9-7 100Base-TX Transmit Packet Deassertion Timing

9.9.8 100Base-TX Transmit Timing (tR/F and Jitter)

Table 9-8 100Base-TX Transmit Timing (tR/F and Jitter)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t1 100Mbs PMD Output Pair tR and tF (1) 3 4 5 ns
100Mbs tR and tF Mismatch(2) 500 ps
t2 100Mbs PMD Output Pair Transmit Jitter 1.4 ns
(1) Rise and fall times taken at 10% and 90% of the +1 or -1 amplitude.
(2) Normal Mismatch is the difference between the maximum and minimum of all rise and fall times.
TLK105 TLK106 t0345-01_lls931.gif Figure 9-8 100Base-TX Transmit Timing (tR/F and Jitter)

9.9.9 100Base-TX Receive Packet Latency Timing

Table 9-9 100Base-TX Receive Packet Latency Timing

PARAMETER TEST CONDITIONS(3) MIN TYP MAX UNIT(2)
t1 Carrier Sense ON Delay(1) 100Mbs Normal mode 14 bits
t2 Receive Data Latency 100Mbs Normal mode 19 bits
t2 Receive data latency(4) 100Mb normal mode with fast RXDV detection ON 15 bits
(1) Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense.
(2) 1 bit time = 10 ns in 100Mbs mode
(3) PMD Input Pair voltage amplitude is greater than the Signal Detect Turn-On Threshold Value.
(4) Fast RXDV detection could be enabled by setting bit[1] of CR1 (address 0x0009).
TLK105 TLK106 t0346-01_lls931.gif Figure 9-9 100Base-TX Receive Packet Latency Timing

9.9.10 100Base-TX Receive Packet Deassertion Timing

Table 9-10 100Base-TX Receive Packet Deassertion Timing

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t1 Carrier Sense OFF Delay(1) 100Mbs Normal mode 19 bits(2)
(1) Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of Carrier Sense.
(2) 1 bit time = 10 ns in 100Mbs mode
TLK105 TLK106 t0347-01_lls931.gif Figure 9-10 100Base-TX Receive Packet Deassertion Timing

9.9.11 10Mbs MII Transmit Timing

Table 9-11 10Mbs MII Transmit Timing

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t1 TX_CLK Low Time 10Mbs MII mode 190 200 210 ns
t2 TX_CLK High Time
t3 TXD[3:0], TX_EN Data Setup to TX_CLK ↑ 10Mbs MII mode 25 ns
t4 TXD[3:0], TX_EN Data Hold from TX_CLK ↑ 10Mbs MII mode 0 ns

An attached Mac should drive the transmit signals using the positive edge of TX_CLK. As shown in Figure 9-11, the MII signals are sampled on the falling edge of TX_CLK.

TLK105 TLK106 tx_tim_lls901.gif Figure 9-11 10Mbs MII Transmit Timing

9.9.12 10Mb/s MII Receive Timing

Table 9-12 10Mb/s MII Receive Timing

PARAMETER(1) TEST CONDITIONS MIN TYP MAX UNIT
t1 RX_CLK High Time 160 200 240 ns
t2 RX_CLK Low Time
t3 RX_CLK rising edge delay from RXD[3:0], RX_DV Valid 10Mbs MII mode 100 ns
t4 RX_CLK to RXD[3:0], RX_DV Delay 10Mbs MII mode 100 ns
(1) RX_CLK may be held low for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated.
TLK105 TLK106 t0349-01_lls931.gif Figure 9-12 10Mb/s MII Receive Timing

9.9.13 10Base-T Transmit Timing (Start of Packet)

Table 9-13 10Base-T Transmit Timing (Start of Packet)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT(1)
t1 Transmit Output Delay from the Falling Edge of TX_CLK 10Mbs MII mode 5.8 bits
(1) (1) 1 bit time = 100ns in 10Mb/s.
TLK105 TLK106 t0352a-01_lls931.gif Figure 9-13 10Base-T Transmit Timing (Start of Packet)

9.9.14 10Base-T Transmit Timing (End of Packet)

Table 9-14 10Base-T Transmit Timing (End of Packet)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t1 End of Packet High Time (with ‘0’ ending bit) 250 310 ns
t2 End of Packet High Time (with ‘1’ ending bit) 250 310 ns
TLK105 TLK106 t0353a-01_lls931.gif Figure 9-14 10Base-T Transmit Timing (End of Packet)

9.9.15 10Base-T Receive Timing (Start of Packet)

Table 9-15 10Base-T Receive Timing (Start of Packet)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t1 Carrier Sense Turn On Delay (PMD Input Pair to CRS) 550 1000 ns
t2 RX_DV Latency(1) 14 bits
t3 Receive Data Latency Measurement shown from SFD 14 bits
(1) 10Base-T RX_DV Latency is measured from first bit of decoded SFD on the wire to the assertion of RX_DV
TLK105 TLK106 rx_latenc_10bt_lls901.gif Figure 9-15 10Base-T Receive Timing (Start of Packet)

9.9.16 10Base-T Receive Timing (End of Packet)

Table 9-16 10Base-T Receive Timing (End of Packet)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t1 Carrier Sense Turn Off Delay 1.8 μs
TLK105 TLK106 t0355a-01_lls931.gif Figure 9-16 10Base-T Receive Timing (End of Packet)

9.9.17 10Mb/s Jabber Timing

Table 9-17 10Mb/s Jabber Timing

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t1 Jabber Activation Time 10 Mb/s MII mode 100 ms
t2 Jabber Deactivation Time 500
TLK105 TLK106 td_10mbs_jabber_lls901.gif Figure 9-17 10Mb/s Jabber Timing

9.9.18 10Base-T Normal Link Pulse Timing

Table 9-18 10Base-T Normal Link Pulse Timing

PARAMETER(1) TEST CONDITIONS MIN TYP MAX UNIT
t1 Pulse Period 10 Mb/s MII mode 16 ms
t2 Pulse Width 100 ns
(1) Transmit timing
TLK105 TLK106 t0358-01_lls931.gif Figure 9-18 10Base-T Normal Link Pulse Timing

9.9.19 Auto-Negotiation Fast Link Pulse (FLP) Timing

Table 9-19 Auto-Negotiation Fast Link Pulse (FLP) Timing

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t1 Clock Pulse to Clock Pulse Period 125 μs
t2 Clock Pulse to Data Pulse Period Data = 1 62 μs
t3 Clock, Data Pulse Width 114 ns
t4 FLP Burst to FLP Burst Period 16 ms
t5 Burst Width 2 ms
TLK105 TLK106 t0359-01_lls931.gif Figure 9-19 Auto-Negotiation Fast Link Pulse (FLP) Timing

9.9.20 100Base-TX Signal Detect Timing

Table 9-20 100Base-TX Signal Detect Timing

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t1 SD Internal Turn-on Time 100 μs
t2 Internal Turn-off Time 200 μs
TLK105 TLK106 t0360-01_lls931.gif

NOTE:

The signal amplitude on PMD Input Pair must be TP-PMD compliant.
Figure 9-20 100Base-TX Signal Detect Timing

9.9.21 100Mbs Loopback Timing

Table 9-21 100Mbs Loopback Timing

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t1 TX_EN to RX_DV Loopback 100Mbs external loopback 241 242 243 ns
100Mbs external loopback – fast RX_DV mode 201 202 203
100Mbs analog loopback 232 233 234
100Mbs PCS Input loop back 120 121 122
100Mbs MII loop back 8 9 10
TLK105 TLK106 t0361-01_lls931.gif
1. Due to the nature of the descrambler function, all 100Base-TX Loopback modes cause an initial dead-time of up to 550 μs during which time no data is present at the receive MII outputs. The 100Base-TX timing specified is based on device delays after the initial 550µs dead-time.
2. Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.
3. External loopback was measured using very short external cable (approximately 10cm).
4. Since MII loopback introduce extreme short roundtrip delay, some hosts would use PCS Input loopback (Mainly in 100BT).
Figure 9-21 100Mbs Loopback Timing

9.9.22 10Mbs Internal Loopback Timing

Table 9-22 10Mbs Internal Loopback Timing

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t1 TX_EN to RX_DV Loopback 10Mbs internal loopback mode 1.7 μs
TLK105 TLK106 t0362-01_lls931.gif
1. Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.
2. Analog loopback was used. Looping the TX to RX at the analog input/output stage.
Figure 9-22 10Mbs Internal Loopback Timing

9.9.23 RMII Transmit Timing

Table 9-23 RMII Transmit Timing

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t1 XI Clock Period 50MHz Reference Clock 20 ns
t2 TXD[1:0] and TX_EN data setup to X1 rising 1.4
t3 TXD[1:0] and TX_EN data hold to X1 rising VDD_IO = 3.3V 2.0
VDD_IO = 2.5V 4.9
t4 XI Clock to PMD Output Pair Latency 12 bits
TLK105 TLK106 TX_timing_lls901.gif Figure 9-23 RMII Transmit Timing

9.9.24 RMII Receive Timing

Table 9-24 RMII Receive Timing

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t1 XI Clock Period 50MHz Reference Clock 20 ns
t2 RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from XI rising 4 10.8 14
t3 CRS ON delay From JK symbol on PMD Receive Pair to initial assertion of CRS_DV 17.6 bits
t4 CRS OFF delay From TR symbol on PMD Receive Pair to initial assertion of CRS_DV 26.2
t5 RXD[1:0] and RX_ER latency From symbol on Receive Pair. * Elasticity buffer set to default value (01) 29.7
t6 RX_CLK Clock Period 50MHz “Recovered clock” while working in “RMII receive clock” mode 20 ns
t7 RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from RX_CLK rising While working in “RMII receive clock” mode 3.8
TLK105 TLK106 RX_timing_lls901.gif Figure 9-24 RMII Receive Timing

NOTE

  1. Per the RMII Specification, output delays assume a 25pF load.
  2. CRS_DV is asserted asynchronously in order to minimize latency of control signals through the PHY. CRS_DV may toggle synchronously at the end of the packet to indicate CRS de-assertion.
  3. RX_DV is synchronous to XI. While not part of the RMII specification, this signal is provided to simplify recovery of receive data.
  4. “RMII receive clock” mode is not part of the RMII specification that allows synchronization of the MAC-PHY RX interface in RMII mode. Setting register 0x000A bit [0] is required to activate this mode.

9.9.25 Isolation Timing

Table 9-25 Isolation Timing

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t1 From Deassertion of S/W or H/W Reset to transition from Isolate to Normal mode 71 ns
TLK105 TLK106 t0365-01_lls931.gif Figure 9-25 Isolation Timing