SBOS551C march   2011  – april 2023 TLV3011-Q1 , TLV3011B-Q1 , TLV3012-Q1 , TLV3012B-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings TLV3012-Q1 DCK Package Only
    2. 6.2  Absolute Maximum Ratings - TLV301x-Q1 DBV Package, TLV3011B-Q1 and TLV3012B-Q1
    3. 6.3  ESD Ratings
    4. 6.4  Thermal Information - TLV3012-Q1 DCK Package Only
    5. 6.5  Thermal Information- TLV301x-Q1 DBV Package, TLV3011B-Q1 and TLV3012B-Q1
    6. 6.6  Recommended Operating Conditions
    7. 6.7  Electrical Characteristics - TLV3012-Q1 DCK Package Only
    8. 6.8  Switching Characteristics - TLV3012-Q1 DCK Package Only
    9. 6.9  Electrical Characteristics- TLV301x-Q1 DBV Package, TLV3011B-Q1 and TLV3012B-Q1
    10. 6.10 Switching Characteristics- TLV301x-Q1 DBV Package, TLV3011B-Q1 and TLV3012B-Q1
  7. 7 Typical Characteristics - TLV3012-Q1 DCK Package Only
  8. 8 Typical Characteristics - TLV301x-Q1 DBV Package, TLV3011B-Q1 and TLV3012B-Q1
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Open Drain Output (TLV3011-Q1 and TLV3011B-Q1)
      2. 9.4.2 Push-Pull Output (TLV3012-Q1 and TLV3012B-Q1)
      3. 9.4.3 Voltage Reference
      4. 9.4.4 TLV3011B-Q1 and TLV3012B-Q1 Fail-Safe inputs
      5. 9.4.5 TLV3011B-Q1 and TLV3012B-Q1 Power On Reset
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 External Hysteresis
      2. 10.1.2 TLV3011B-Q1 and TLV3012B-Q1 Hysteresis
    2. 10.2 Typical Application
      1. 10.2.1 Under-Voltage Detection
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
    3. 10.3 System Examples
      1. 10.3.1 Power-On Reset
      2. 10.3.2 Relaxation Oscillator
    4. 10.4 Power Supply Recommendations
    5. 10.5 Layout
      1. 10.5.1 Layout Guidelines
      2. 10.5.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.2.1.2 Detailed Design Procedure

Configure the circuit as shown in Figure 10-3. Connect (V+) to VBAT which also powers the microcontroller. Resistors R1 and R2 create the under-voltage alert level of 2.0 V. When the battery voltage sags down to 2.0 V, the resistor divider voltage crosses VREF, the 1.242 V reference threshold of the TLV3012-Q1. This causes the comparator output to transition from a logic high to a logic low. The push-pull output of the TLV3012-Q1 is selected since the comparator operating voltage is shared with the microcontroller which is receiving the under-voltage alert signal.

Equation 2 is derived from the analysis of Figure 10-3.

Equation 2. GUID-BF73EAE3-28A3-4D37-9E64-671E1617EBF6-low.gif

where

  • R1 and R2 are the resistor values for the resistor divider connected to IN+
  • VBAT is the voltage source that is being monitored for an undervoltage condition.
  • VREF is the falling edge threshold where the comparator output changes state from high to low

Rearranging Equation 2 and solving for R1 yields Equation 3.

Equation 3. GUID-C276625F-6072-4AC1-88DF-9AE113AC3EF2-low.gif

For the specific undervoltage detection of 2.0 V using the TLV3012-Q1, the following results are calculated.

Equation 4. GUID-8D580C3A-0B98-43CD-B71B-40917E3FB5D2-low.gif

where

  • R2 is set to 1 MΩ
  • VBAT is set to 2.0 V
  • VREF is set to1.242 V

Choose RTOTAL (R1 + R2) such that the current through the divider is at least 100 times higher than the input bias current (IBIAS). The resistors can have high values to minimize current consumption in the circuit without adding significant error to the resistive divider.