SBOS551D March   2011  – January 2025 TLV3011-Q1 , TLV3011B-Q1 , TLV3012-Q1 , TLV3012B-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Thermal Information
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Open Drain Output (TLV3011-Q1 and TLV3011B-Q1)
      2. 7.4.2 Push-Pull Output (TLV3012-Q1 and TLV3012B-Q1)
      3. 7.4.3 Voltage Reference
      4. 7.4.4 Internal Hysteresis
      5. 7.4.5 TLV3011B-Q1 and TLV3012B-Q1 Fail-Safe inputs
      6. 7.4.6 TLV3011B-Q1 and TLV3012B-Q1 Power On Reset
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adding External Hysteresis
    2. 8.2 Typical Application
      1. 8.2.1 Under-Voltage Detection
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 System Examples
      1. 8.3.1 Power-On Reset
      2. 8.3.2 Relaxation Oscillator
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

For VS (TOTAL SUPPLY VOLTAGE) = (V+) – (V–) = 1.8V and 5.5V,  VCM = V/2 at TA = 25°C (Unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VCM = (V–) –6 ±0.3 6 mV
VOS Input offset voltage VCM = (V–)
TA = –40°C to +125°C
–9 9 mV
dVIO/dT Input offset voltage drift VCM = (V–)
TA = –40°C to +125°C
±12 µV/°C
PSRR power supply rejection ratio VCM = (V–)
VS = 1.8V to 5.5V
TA = –40°C to +125°C
100 1000 µV/V
PSRR power supply rejection ratio
(B-Versions)
VCM = (V–)
VS = 1.65V to 5.5V
TA = –40°C to +125°C
100 1000 µV/V
VHYS Input hysteresis voltage TA = –40°C to +125°C 2 6 8 mV
INPUT BIAS CURRENT
IB Input bias current VCM =  V/2  –10(1) ±4.5 10(1) pA
IOS Input offset current VCM =  V/2  –10(1) ±1 10(1) pA
INPUT COMMON MODE RANGE
VCM-Range Common-mode voltage range VS = 1.8V to 5.5V (V–) – 0.2 (V+) + 0.2 V
CMRR Common mode rejection ratio VCM = (V–) + 1.5V to (V+) + 0.2V
VS = 5.5V
60 74 dB
CMRR Common mode rejection ratio VCM = (V–) - 0.2V to (V+) + 0.2V
VS = 5.5V
54 62 dB
RCM Input Common Mode Resistance 1013
CIC Input Common Mode Capacitance 2 pF
INPUT IMPEDANCE
RDM Input Differential Mode Resistance 1013
CID Input Differential Mode  Capacitance 4 pF
OUTPUT
VOL Voltage swing from (V–) VS = 5V
ISINK = 5mA
TA = –40°C to +125°C
160 200 mV
VOH Voltage swing from (V+)
(for Push-Pull only)
VS = 5V
ISOURCE = 5mA
TA = –40°C to +125°C
90 200 mV
VOLTAGE REFERENCE
VOUT Reference Voltage 1.223 1.242 1.260 V
Accuracy ±0.25% ±1.5%
dVOUT/dT Temperature Drift TA = –40°C to +125°C 40 100 ppm/℃
dVOUT/dILOAD Load Regulation, Sourcing 0mA < ISOURCE ≤ 0.5mA 0.36 1(1) mV/mA
Load Regulation, Sinking 0mA < ISINK ≤ 0.5mA 6.6
mV/mA

ILOAD Output Current 0.5 mA
dVOUT/dVS Line Regulation 1.8V ≤ VS ≤ 5.5V 10 100(1) µV/V
dVOUT/dVS Line Regulation
(B-Versions)
1.65V ≤ VS ≤ 5.5V 10 100(1) µV/V
Vnoise Noise f = 0.1Hz to 10Hz 0.2 mVPP
POWER SUPPLY
IQ Quiescent current per comparator Output is logic high 2.8 5 µA
IQ Quiescent current per comparator Output is logic high
TA = –40°C to +125°C
7 µA
IQ Quiescent current per comparator
(B-Versions)
Output is logic high 2.4 3.1 µA
IQ Quiescent current per comparator
(B-Versions)
Output is logic high
TA = –40°C to +125°C
3.6 µA
Verified by characterization