SLAS548D October   2008  – September 2015 TLV320ADC3001

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  Dissipation Ratings
    7. 8.7  I2S/LJF/RJF Timing in Master Mode
    8. 8.8  DSP Timing in Master Mode
    9. 8.9  I2S/LJF/RJF Timing in Slave Mode
    10. 8.10 DSP Timing in Slave Mode
    11. 8.11 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Hardware Reset
      2. 10.3.2  PLL Start-up
      3. 10.3.3  Software Power Down
      4. 10.3.4  miniDSP
      5. 10.3.5  Audio Data Converters
      6. 10.3.6  Digital Audio Data Serial Interface
        1. 10.3.6.1 Right-Justified Mode
        2. 10.3.6.2 Left-Justified Mode
        3. 10.3.6.3 I2S Mode
        4. 10.3.6.4 DSP Mode
      7. 10.3.7  Audio Clock Generation
      8. 10.3.8  Stereo Audio ADC
      9. 10.3.9  Audio Analog Inputs
        1. 10.3.9.1 Digital Volume Control
        2. 10.3.9.2 Fine Digital Gain Adjustment
        3. 10.3.9.3 AGC
      10. 10.3.10 Input Impedance and VCM Control
      11. 10.3.11 MICBIAS Generation
      12. 10.3.12 ADC Decimation Filtering and Signal Processing
        1. 10.3.12.1 Processing Blocks
        2. 10.3.12.2 Processing Blocks - Details
          1. 10.3.12.2.1 First-Order IIR, AGC, Filter A
          2. 10.3.12.2.2 Five Biquads, First-Order IIR, AGC, Filter A
          3. 10.3.12.2.3 25-Tap FIR, First-Order IIR, AGC, Filter A
          4. 10.3.12.2.4 First-Order IIR, AGC, Filter B
          5. 10.3.12.2.5 Three Biquads, First-Order IIR, AGC, Filter B
          6. 10.3.12.2.6 20-Tap FIR, First-Order IIR, AGC, Filter B
          7. 10.3.12.2.7 First-Order IIR, AGC, Filter C
          8. 10.3.12.2.8 Five Biquads, First-Order IIR, AGC, Filter C
          9. 10.3.12.2.9 25-Tap FIR, First-Order IIR, AGC, Filter C
        3. 10.3.12.3 User-Programmable Filters
          1. 10.3.12.3.1 First-Order IIR Section
          2. 10.3.12.3.2 Biquad Section
          3. 10.3.12.3.3 FIR Section
        4. 10.3.12.4 Decimation Filter
          1. 10.3.12.4.1 Decimation Filter A
          2. 10.3.12.4.2 Decimation Filter B
          3. 10.3.12.4.3 Decimation Filter C
    4. 10.4 Device Functional Modes
      1. 10.4.1 Recording Mode
    5. 10.5 Programming
      1. 10.5.1 Digital Interfaces
        1. 10.5.1.1 I2C Control Mode
    6. 10.6 Register Maps
      1. 10.6.1 Control Registers
      2. 10.6.2 Control Registers, Page 0: Clock Multipliers and Dividers, Serial Interfaces, Flags, Interrupts and Programming of GPIOs
      3. 10.6.3 CONTROL REGISTERS Page 1: ADC Routing, PGA, Power-Controls, Etc.
      4. 10.6.4 Control Registers, Page 4: ADC Digital Filter Coefficients
      5. 10.6.5 Control Registers, Page 5: ADC Programmable Coefficients RAM (65:127)
      6. 10.6.6 Control Registers, Page 32: ADC DSP Engine Instruction RAM (0:31)
        1. 10.6.6.1 Page 32 / Register 5 Through Page 32 / Register 97
      7. 10.6.7 Control Registers, Page 33 Through Page 47: ADC DSP Engine Instruction RAM (32:63) Through (480:511)
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 ADC Setup
          1. 11.2.2.1.1 Step 1
          2. 11.2.2.1.2 Step 2
          3. 11.2.2.1.3 Example Register Setup to Record Analog Data Through ADC to Digital Out
        2. 11.2.2.2 MICBIAS
        3. 11.2.2.3 Decoupling Capacitors
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Community Resources
    2. 14.2 Trademarks
    3. 14.3 Electrostatic Discharge Caution
    4. 14.4 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

11.1 Application Information

This typical connection diagram highlights the required external components and system level connections for proper operation of the device in several popular use cases. Each of these configurations can be realized using the Evaluation Modules (EVMs) for the device. These flexible modules allow full evaluation of the device in the most common modes of operation. Any design variation can be supported by TI through schematic and layout reviews. Visit www.e2e.ti.com for design assistance and join the audio amplifier discussion forum for additional information.

11.2 Typical Application

TLV320ADC3001 typ_conn_las548.gifFigure 44. Typical Connections

11.2.1 Design Requirements

Table 15 lists the design parameters for this example.

Table 15. Design Parameters

KEY PARAMETER SPECIFICATION/UNIT
AVDD 3.3 V
AVDD Supply Current > 6 mA (PLL on, AGC off, miniDSP off, stereo record, fs = 48 kHz)
DVDD 1.8 V
DVDD Supply Current > 4 mA (PLL on, AGC off, miniDSP off, stereo record, fs = 48 kHz)
IOVDD 1.8 V
Max. MICBIAS Current 4 mA (MICBIAS voltage 2.5 V)

11.2.2 Detailed Design Procedure

11.2.2.1 ADC Setup

The following paragraphs are intended to guide a user through the steps necessary to configure the TLV320ADC3001.

11.2.2.1.1 Step 1

The system clock source (master clock) and the targeted ADC sampling frequency must be identified.

Depending on the targeted performance, the decimation filter type (A, B, or C) and AOSR value can be determined:

  • Filter A must be used for 48-kHz high-performance operation; AOSR must be a multiple of 8.
  • Filter B must be used for up to 96-kHz operations; AOSR must be a multiple of 4.
  • Filter C must be used for up to 192-kHz operations; AOSR must be a multiple of 2.

In all cases, AOSR is limited in its range by the following condition:

Equation 6. 2.8 MHz < AOSR × ADC_fS < 6.2 MHz

Based on the identified filter type and the required signal-processing capabilities, the appropriate processing block can be determined from the list of available processing blocks (PRB_R4 to PRB_R18).

Based on the available master clock, the chosen AOSR and the targeted sampling rate, the clock divider values NADC and MADC can be determined. If necessary, the internal PLL can add a large degree of flexibility.

In summary, ADC_CLKIN (derived directly from the system clock source or from the internal PLL) divided by MADC, NADC, and AOSR must be equal to the ADC sampling rate ADC_fS. The ADC_CLKIN clock signal is shared with the DAC clock-generation block.

Equation 7. ADC_CLKIN = NADC × MADC × AOSR × ADC_fS

To a large degree, NADC and MADC can be chosen independently in the range of 1 to 128. In general, NADC must be as large as possible as long as the following condition can still be met:

Equation 8. MADC × AOSR / 32 ≥ RC

RC is a function of the chosen processing block and is listed in the Resource Class column of Table 6.

The common-mode voltage setting of the device is determined by the available analog power supply.

At this point, the following device-specific parameters are known: PRB_Rx, AOSR, NADC, MADC, input and output common-mode values. If the PLL is used, the PLL parameters P, J, D, and R are determined as well.

11.2.2.1.2 Step 2

Setting up the device via register programming:

The following list gives a sequence of items that must be executed in the time between powering the device up and reading data from the device:

  1. Define starting point:
    1. Power up applicable external hardware power supplies
    2. Set register page to 0
    3. Initiate SW reset
  2. Program clock settings
    1. Program PLL clock dividers P, J, D, and R (if PLL is used)
    2. Power up PLL (if PLL is used)
    3. Program and power up NADC
    4. Program and power up MADC
    5. Program OSR value
    6. Program I2S word length if required (for example, 20 bits)
    7. Program the processing block to be used
  3. Program analog blocks
    1. Set register page to 1
    2. Program MICBIAS if applicable
    3. Program MicPGA
    4. Program routing of inputs/common mode to ADC input
    5. Unmute analog PGAs and set analog gain
  4. Program ADC
    1. Set register page to 0
    2. Power up ADC channel
    3. Unmute digital volume control and set gain

A detailed example can be found in Example Register Setup to Record Analog Data Through ADC to Digital Out.

11.2.2.1.3 Example Register Setup to Record Analog Data Through ADC to Digital Out

A typical EVM I2C register control script follows to show how to set up the TLV320ADC3001 in record mode with fS = 44.1 kHz and MCLK = 11.2896 MHz.


# Key: w 30 XX YY ==> write to I2C address 0x30, to register 0xXX, data 0xYY
# # ==> comment delimiter
# # The following list gives an example sequence of items that must be executed in the time # between powering the device up and reading data from the device. Note that there are # other valid sequences depending on which features are used. # # ADC3101EVM Key Jumper Settings and Audio Connections: # 1. Remove Jumpers W12 and W13 # 2. Insert Jumpers W4 and W5 # 3. Insert a 3.5mm stereo audio plug into J9 for # single-ended input IN1L(P) - left channel and # single-ended input IN1R(M) - right channel ################################################################ # 1. Define starting point: # (a) Power up appicable external hardware power supplies # (b) Set register page to 0 # w 30 00 00 # (c) Initiate SW Reset # w 30 01 01 # # 2. Program Clock Settings # (a) Program PLL clock dividers P,J,D,R (if PLL is necessary) # # In EVM, the ADC3001 receives: MCLK = 11.2896 MHz, # BCLK = 2.8224 MHz, WCLK = 44.1 kHz # # Sinve the sample rate is a multiple of the input MCLK then # no PLL is needed thereby saving power. Use Default (Reset) Settings: # ADC_CLKIN = MCLK, P=1, R=1, J=4, D=0000 w 30 04 00 w 30 05 11 w 30 06 04 w 30 07 00 w 30 08 00 # # (b) Power up PLL (if PLL is necessary) - Not Used in this Example w 30 05 11 # (c) Program and power up NADC # # NADC = 1, divider powered on w 30 12 81 # # (d) Program and power up MADC # # MADC = 2, divider powered on w 30 13 82 # # (e) Program OSR value # # AOSR = 128 (default) w 30 14 80 # # (f) Program I2S word length as required (16, 20, 24, 32 bits) # # mode is i2s, wordlength is 16, slave mode (default) w 30 1B 00 # # (g) Program the processing block to be used # # PRB_P1 w 30 3d 01 # # 3. Program Analog Blocks # (a) Set register Page to 1 # w 30 00 01 # # (b) Program MICBIAS if appicable # # Not used (default) w 30 33 00 # # (c) Program MicPGA # # Left Analog PGA Seeting = 0dB w 30 3b 00 # # Right Analog PGA Seeting = 0dB w 30 3c 00 # # (d) Routing of inputs/common mode to ADC input # (e) Unmute analog PGAs and set analog gain # # Left ADC Input selection for Left PGA = IN1L(P) as Single-Ended w 30 34 fc # # Right ADC Input selection for Right PGA = IN1R(M) as Single-Ended w 30 37 fc # # 4. Program ADC # # (a) Set register Page to 0 # w 30 00 00 # # (b) Power up ADC channel # # Power-up Left ADC and Right ADC w 30 51 c2 # # (c) Unmute digital volume control and set gain = 0 dB # # UNMUTE w 30 52 00 #

11.2.2.2 MICBIAS

TLV320ADC3001 has a built-in bias voltage output for biasing of microphones. No intentional capacitors must be connected directly to the MICBIAS output for filtering.

11.2.2.3 Decoupling Capacitors

The TLV320ADC3001 requires adequate power supply decoupling to ensure that the noise and total harmonic distortion (THD) are low. A good ceramic capacitor, typically 0.1 µF, placed as close as possible to the device AVDD, IOVDD and DVDD lead works best. Placing this decoupling capacitor close to the TLV320ADC3001 is important for the performance of the converter. For filtering lower-frequency noise signals, a 1 µF or greater capacitor placed near the device would also help.

11.2.3 Application Curves

Table 16 lists the application curves in the Typical Characteristics section.

Table 16. Table of Graphs

GRAPH TITLE FIGURE
Line Input to ADC FFT Plot Figure 8
Input-Referred Noise vs. PGA Gain Figure 9