SLAS666B January 2010 – October 2018 TLV320DAC3101
PRODUCTION DATA.
The device has an integrated class-D stereo speaker driver (SPLP/SPLM and SPRP/SPRM) capable of driving an 8-Ω differential load. The speaker driver can be powered directly from the battery supply (2.7 V to 5.5 V) on the SPLVDD and SPRVDD pins; however, the voltage (including spike voltage) must be limited below the absolute-maximum voltage of 6 V.
The speaker driver is capable of supplying 400 mW per channel with a 3.6-V power supply. Through the use of digital mixing, the device can connect one or both digital audio playback data channels to either speaker driver; this also allows digital channel swapping if needed.
The left class-D speaker driver can be powered on by writing to page 1 / register 32, bit D7. The right class-D speaker driver can be powered on by writing to page 1 / register 32, bit D6. The left-output driver gain can be controlled by writing to page 1 / register 42, bits D4–D3, and it can be muted by writing to page 1 / register 42, bit D2. The right-output driver gain can be controlled by writing to page 1 / register 43, bits D4–D3, and it can be muted by writing to page 1 / register 43, bit D2.
The device has a short-circuit protection feature for the speaker drivers that is always enabled to provide protection. If the output is shorted, the output stage shuts down on the overcurrent condition. (Current limiting is not an available option for the higher-current speaker driver output stage.) In case of a short circuit on either channel, the output is disabled and a status flag is provided as a read-only bit on page 1 / register 32, bit D0.
If shutdown occurs because of an overcurrent condition, then the device requires a reset to re-enable the output stage. Resetting occurs in two ways. First, the device master reset can be used, which requires either toggling the RESET pin or using the software reset. If master reset is used, it resets all of the registers. Second, a dedicated speaker power-stage reset can be used that keeps all of the other device settings. The speaker power-stage reset occurs by setting page 1 / register 32, bit D7 for SPLP and SPLM and by setting page 1 / register 32, bit D6 for SPRP and SPRM. If the fault condition has been removed, then the device returns to normal operation. If the fault is still present, then another shutdown occurs. Repeated resetting (more than three times) is not recommended as this could lead to overheating.
To minimize battery current leakage, the SPLVDD and SPRVDD voltage levels must not be less than the AVDD voltage level.
The device has a thermal protection (OTP) feature for the speaker drivers which is always enabled to provide protection. If the device overheats, then the output stops switching. When the device cools down, the device resumes switching. An overtemperature status flag is provided as a read-only bit on page 0 / register 3, bit D1. The OTP feature is for self-protection of the device. If die temperature can be controlled at the system or board level, then overtemperature does not occur.