SLVSBC1D October   2013  – October 2016 TLV62565 , TLV62566

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 Power Save Mode
      2. 9.3.2 Enabling/Disabling the Device
      3. 9.3.3 Soft Start
      4. 9.3.4 Switch Current Limit
      5. 9.3.5 Power Good
    4. 9.4 Device Functional Modes
      1. 9.4.1 Under Voltage Lockout
      2. 9.4.2 Thermal Shutdown
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Output Filter Design
        2. 10.2.1.2 Inductor Selection
        3. 10.2.1.3 Input and Output Capacitor Selection
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Setting the Output Voltage
        2. 10.2.2.2 Loop Stability
      3. 10.2.3 Application Performance Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Related Links
    4. 13.4 Receiving Notification of Documentation Updates
    5. 13.5 Community Resources
    6. 13.6 Trademarks
    7. 13.7 Electrostatic Discharge Caution
    8. 13.8 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Layout

12.1 Layout Guidelines

The PCB layout is an important step to maintain the high performance of the TLV62565 devices.

  • The input/output capacitors and the inductor should be placed as close as possible to the IC. This keeps the traces short. Routing these traces direct and wide results in low trace resistance and low parasitic inductance.
  • A common power GND should be used.
  • The low side of the input and output capacitors must be connected properly to the power GND to avoid a GND potential shift.
  • The sense traces connected to FB are signal traces. Special care should be taken to avoid noise being induced. Keep these traces away from SW nodes.
  • GND layers might be used for shielding.

12.2 Layout Example

TLV62565 TLV62566 TLV62565_layout_SLVSBC1.gif Figure 22. TLV62565/6 Layout

12.3 Thermal Considerations

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of a given component.

Two basic approaches for enhancing thermal performance are listed below:

  • Improving the power dissipation capability of the PCB design
  • Introducing airflow in the system

For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics Application Notes SZZA017 and SPRA953.