SBOS817I June 2017 – August 2021 TLV6741 , TLV6742
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
OFFSET VOLTAGE | ||||||||
VOS | Input offset voltage | VS = 5.0 V | ±0.15 | ±1.0 | mV | |||
TA = –40°C to 125°C | TLV6742/4(3) | ±1.2 | ||||||
dVOS/dT | Input offset voltage drift | TA = –40°C to 125°C | TLV6741(2) | ±0.35 | µV/℃ | |||
TLV6742/4(3) | ±0.2 | |||||||
PSRR | Input offset voltage versus power supply | VCM = V– | TLV6741(2) | ±0.32 | ±6.3 | μV/V | ||
VCM = V– | TLV6742/4(3) | ±0.7 | ±5.8 | |||||
Channel separation | f = 20 kHz | 130 | dB | |||||
INPUT BIAS CURRENT | ||||||||
IB | Input bias current | TLV6741(2) | ±10 | pA | ||||
TLV6742/4(3) | ±3 | |||||||
IOS | Input offset current | TLV6741(2) | ±10 | pA | ||||
TLV6742/4(3) | ±0.5 | |||||||
NOISE | ||||||||
EN | Input voltage noise | f = 0.1 to 10 Hz | 1.2 | μVPP | ||||
0.227 | µVRMS | |||||||
eN | Input voltage noise density | f = 10 Hz | TLV6742/4(3) | 30 | nV/√Hz | |||
f = 1 kHz | TLV6741(2) | 5.0 | ||||||
TLV6742/4(3) | 4.6 | |||||||
f = 10 kHz | TLV6741(2) | 3.7 | ||||||
TLV6742/4(3) | 3.5 | |||||||
iN | Input current noise | f = 1 kHz | 23 | fA/√Hz | ||||
INPUT VOLTAGE RANGE | ||||||||
VCM | Common-mode voltage range | (V–) | (V+) -1.2 | V | ||||
CMRR | Common-mode rejection ratio | (V–) < VCM < (V+) – 1.2 V | TLV6741(2) | 95 | 120 | dB | ||
VS = 1.8 V, (V–) < VCM < (V+) – 1.2 V | TLV6742/4(3) | 87 | 100 | |||||
VS = 5.5, (V–) < VCM < (V+) – 1.2 V | 94 | 110 | ||||||
INPUT CAPACITANCE | ||||||||
ZID | Differential | 10 || 6 | MΩ || pF | |||||
ZICM | Common-mode | 10 || 6 | GΩ || pF | |||||
OPEN-LOOP GAIN | ||||||||
AOL | Open-loop voltage gain | (V–) + 40 mV < VO < (V+) – 40 mV, RL = 10 kΩ to VS/2 | TLV6741(2) | 125 | dB | |||
(V–) + 150 mV < VO < (V+) – 150 mV, RL = 2 kΩ to VS/2 | 110 | 130 | ||||||
VS= 1.8 V, (V–) + 150 mV < VO < (V+) – 150 mV, RL = 2 kΩ to VS/2 | TLV6742/4(3) | 107 | 120 | |||||
VS= 5.5 V, (V–) + 150 mV < VO < (V+) – 150 mV, RL = 2 kΩ to VS/2 | 140 | |||||||
VS = 1.8 V, (V–) + 40m V < VO < (V+) – 40 mV, RL = 10 kΩ to VS/2 | 110 | 120 | ||||||
VS = 5.5 V, (V–) + 40m V < VO < (V+) – 40 mV, RL = 10 kΩ to VS/2 | 140 | |||||||
FREQUENCY RESPONSE | ||||||||
GBW | Gain-bandwidth product | 10 | MHz | |||||
SR | Slew rate | VS = 5.5 V, G = +1, CL = 20 pF | 4.5 | V/μs | ||||
tS | Settling time | To 0.1%, VS = 5.5 V, VSTEP = 2 V, G = +1, CL = 20pF | 0.65 | μs | ||||
To 0.01%, VS = 5.5 V, VSTEP = 2 V, G = +1, CL = 20pF | 1.2 | |||||||
Phase margin | G = +1, RL = 10kΩ, CL = 20 pF | 55 | ° | |||||
Overload recovery time | VIN × gain > VS | 0.2 | μs | |||||
THD+N | Total harmonic distortion + noise | VS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = +1, f = 1 kHz, RL = 10 kΩ | TLV6741(2) | 0.00035% | ||||
TLV6742/4(3) | 0.00015% | |||||||
EMIRR | Electro-magnetic interference rejection ratio | f = 1 GHz | TLV6742/4(3) | 51 | dB | |||
OUTPUT | ||||||||
Voltage output swing from rail | Positive/Negative rail headroom | VS = 5.5 V, RL = 10k | TLV6741(2) | 8 | 10 | mV | ||
Positive rail headroom | VS = 5.5 V, RL = no load | TLV6742/4(3) | 7 | |||||
VS = 5.5 V, RL = 2 kΩ | 35 | |||||||
VS = 5.5 V, RL = 10 kΩ | 5 | 14 | ||||||
Negative rail headroom | VS = 5.5 V, RL = no load | 7 | ||||||
VS = 5.5 V, RL = 2 kΩ | 35 | |||||||
VS = 5.5 V, RL = 10 kΩ | 5 | 14 | ||||||
ISC | Short-circuit current | TLV6742/4(3) | ±68 | mA | ||||
CLOAD | Capacitive load drive | See Figure 7-58 | ||||||
ZO | Open-loop output impedance | f = 10 MHz, IO = 0 A | TLV6741(2) | 160 | Ω | |||
f = 2 MHz, IO = 0 A | TLV6742/4(3) | 165 | ||||||
POWER SUPPLY | ||||||||
IQ | Quiescent current per amplifier | VS = 5.5 V, IO = 0 A | TLV6741(2) | 890 | µA | |||
TA = –40°C to 125°C | 1100 | |||||||
TLV6742/4(3) | 990 | 1200 | ||||||
TA = –40°C to 125°C | 1250 | |||||||
Turn-On Time | At TA = 25°C, VS = 5.5 V, VS ramp rate > 0.3 V/µs | TLV6742/4(3) | 10 | μs | ||||
SHUTDOWN | ||||||||
IQSD | Quiescent current per amplifier | All amplifiers disabled, SHDN = V– | 1 | 3.5 | µA | |||
ZSHDN | Output impedance during shutdown | Amplifier disabled | 10 || 6 | GΩ || pF | ||||
VIH | Logic high threshold voltage (amplifier enabled) | (V–) + 1.1 V | V | |||||
VIL | Logic low threshold voltage (amplifier disabled) | (V–) + 0.2 V | ||||||
tON | Amplifier enable time (full shutdown) (1) | G = +1, VCM = V-, VO = 0.1 × VS/2 | 15 | µs | ||||
Amplifier enable time (partial shutdown)(2) | G = +1, VCM = V-, VO = 0.1 × VS/2 | 8 | ||||||
tOFF | Amplifier disable time (1) | VCM = V-, VO = VS/2 | 3 | |||||
SHDN pin input bias current (per pin) | (V+) ≥ SHDN ≥ (V–) + 0.9 V | 0.4 | µA | |||||
(V–) ≤ SHDN ≤ (V–) + 0.7 V | 0.25 |