SBVS323 Data sheet

SBVS323 September 2017 TLV742P

PRODUCTION DATA.

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

DQN|4

Thermal pad, mechanical data (Package|Pins)

DQN|4
- QFND355C

Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TLV742P is a LDO with low quiescent current that delivers excellent line and load transient performance. This LDO regulator offers current limit and thermal protection. The operating junction temperature of this device series is –40°C to +125°C.

8.2 Typical Application

Figure 44. Typical Application Circuit

8.2.1 Design Requirements

Provide an input supply with adequate headroom to meet minimum V_INrequirements (as listed in Table 1), compensate for the GND pin current, and to power the load.

Table 1. Design Parameters

PARAMETER	DESIGN REQUIREMENT
Input voltage	1.8 V to 3.6 V
Output voltage	1.2 V
Output current	100 mA

8.2.2 Detailed Design Procedure

8.2.2.1 Input and Output Capacitor Requirements

Generally, 1-µF X5R- and X7R-type ceramic capacitors are recommended because these capacitors have minimal variation in value and equivalent series resistance (ESR) over temperature.

However, the TLV742P is designed to be stable with an effective capacitance of 0.1 µF or larger at the output. As a result, the device is stable with capacitors of other dielectric types if the effective capacitance under operating bias voltage and temperature is greater than 0.1 µF. This effective capacitance refers to the capacitance that the LDO detects under operating bias voltage and temperature conditions; that is, the capacitance after taking bias voltage and temperature derating into consideration. In addition to using less expensive dielectrics, this stability with 0.1-µF effective capacitance enables the use of smaller footprint capacitors that have higher derating in size- and space-constrained applications.

Using a 0.1-µF rated capacitor at the output of the LDO does not ensure stability because the effective capacitance under the specified operating conditions is less than 0.1 µF. Maximum ESR must be less than
200 mΩ.

Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1-µF to
1-µF, low ESR capacitor across the IN pin and GND pin of the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be required if large, fast rise-time load transients are anticipated, or if the device is not located close to the power source. If source impedance is more than 2-Ω, a 0.1-µF input capacitor may be required to ensure stability.

8.2.2.2 Dropout Voltage

The TLV742P series of LDOs use a PMOS pass transistor to achieve low dropout. When (V_IN – V_OUT) is less than the dropout voltage (V_DO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the R_DS(ON) of the PMOS pass element. V_DO scales approximately with output current because the PMOS device functions similar to a resistor in dropout.

PSRR and transient response degrade when (V_IN – V_OUT) approaches dropout.