SBOSAD7A April   2023  – August 2024 TLV9161-Q1 , TLV9162-Q1 , TLV9164-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for Single Channel
    5. 5.5 Thermal Information for Dual Channel
    6. 5.6 Thermal Information for Quad Channel
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Protection Circuitry
      2. 6.3.2 EMI Rejection
      3. 6.3.3 Thermal Protection
      4. 6.3.4 Capacitive Load and Stability
      5. 6.3.5 Common-Mode Voltage Range
      6. 6.3.6 Phase Reversal Protection
      7. 6.3.7 Electrical Overstress
      8. 6.3.8 Overload Recovery
      9. 6.3.9 Typical Specifications and Distributions
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Low-Side Current Measurement
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 TINA-TI (Free Software Download)
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Electrical Characteristics

For VS = (V+) – (V–) = 2.7V to 16V (±1.35V to ±8V) at TA = 25°C, RL = 10kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VCM = V– ±0.21 ±1.03 mV
TA = –40°C to 125°C ±1.2
dVOS/dT Input offset voltage drift VCM = V– TA = –40°C to 125°C ±0.25 µV/℃
PSRR Input offset voltage versus power supply TLV9161-Q1, TLV9162-Q1, VCM = V–, VS = 5V to 16V ±0.45 ±2 μV/V
TLV9161-Q1, TLV9162-Q1 D and DGK packages
VCM = V–, VS = 5V to 16V		 TA = –40°C to 125°C ±0.45 ±3
TLV9162-Q1 PW package
VCM = V–, VS = 5V to 16V		 TA = –40°C to 125°C ±0.45 ±3.8
TLV9164-Q1, VCM = V–, VS = 5V to 16V ±0.45 ±2.2
TA = –40°C to 125°C ±0.45 ±3.8
TLV9161-Q1, TLV9162-Q1, TLV9164-Q1, VCM = V–, VS = 2.7V to 16V(1) TA = –40°C to 125°C ±2 ±12
DC channel separation 0.4 µV/V
INPUT BIAS CURRENT
IB Input bias current ±10 pA
IOS Input offset current ±10 pA
NOISE
EN Input voltage noise f = 0.1Hz to 10Hz 2.7 μVPP
0.49 µVRMS
eN Input voltage noise density f = 1kHz 6.8 nV/√Hz
f = 10kHz 4.2
iN Input current noise density f = 1kHz 55 fA/√Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (V–) (V+) V
CMRR Common-mode rejection ratio VS = 16V, V– < VCM < (V+) – 2V (PMOS pair) TA = –40°C to 125°C 85 110 dB
VS = 5V, V– < VCM < (V+) – 2V (PMOS pair)(1) 75 98
VS = 2.7V, V– < VCM < (V+) – 2V (PMOS pair) 90
VS = 2.7 – 16V, (V+) – 1V < VCM < V+ (NMOS pair) 78
(V+) – 2V < VCM < (V+) – 1V See Figure 5-6
INPUT IMPEDANCE
ZID Differential 100 || 9 MΩ || pF
ZICM Common-mode 6 || 1 TΩ || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 16V, VCM = VS / 2,
(V–) + 0.1V < VO < (V+) –  0.1V		 120 136 dB
TA = –40°C to 125°C 136
VS = 5V, VCM = VS / 2,
(V–) + 0.1V < VO < (V+) –  0.1V(1)		 104 125
TA = –40°C to 125°C 125
VS = 2.7V, VCM = VS / 2,
(V–) + 0.1V < VO < (V+) –  0.1V(1)		 90 105
TA = –40°C to 125°C 105
FREQUENCY RESPONSE
GBW Gain-bandwidth product 11 MHz
SR Slew rate VS = 16V, G = +1, VSTEP = 10V, CL = 20pF(2) 33 V/μs
tS Settling time To 0.1%, VS = 16V, VSTEP = 10V, G = +1, CL = 20pF 0.70 μs
To 0.1%, VS = 16V, VSTEP = 2V, G = +1, CL = 20pF 0.22
To 0.01%, VS = 16V, VSTEP = 10V, G = +1, CL = 20pF 0.89
To 0.01%, VS = 16V, VSTEP = 2V, G = +1, CL = 20pF 0.42
Phase margin G = +1, RL = 10kΩ, CL = 20pF 64 °
Overload recovery time VIN  × gain > VS 120 ns
THD+N Total harmonic distortion + noise VS = 16V, VO = 3VRMS, G = 1, f = 1kHz 0.00005%
126 dB
VS = 10V, VO = 3VRMS, G = 1, f = 1kHz, RL = 128Ω 0.0032%
90 dB
VS = 10V, VO = 0.4VRMS, G = 1, f = 1kHz, RL = 32Ω 0.00032%
110 dB
OUTPUT
  Voltage output swing from rail Positive and negative
rail headroom		 VS = 16V, RL = no load   6 mV
VS = 16V, RL = 10kΩ   25 60
VS = 16V, RL = 2kΩ   85 300
VS = 2.7V, RL = no load   0.5
VS = 2.7V, RL = 10kΩ   5 20
VS = 2.7V, RL = 2kΩ   20 50
ISC Short-circuit current ±73 mA
CLOAD Capacitive load drive See Figure 5-33 pF
ZO Open-loop output impedance IO = 0A See Figure 5-30 Ω
POWER SUPPLY
IQ Quiescent current per amplifier TLV9162-Q1, TLV9164-Q1, IO = 0A 2.4 2.8 mA
TA = –40°C to 125°C 2.84
TLV9161-Q1, IO = 0A 2.48 2.92
TA = –40°C to 125°C 2.98
(1) Specified by characterization only.
(2) See Figure 5-15 for more information.