SBOS581B September 2011 – June 2022 TMP100-Q1 , TMP101-Q1
PRODUCTION DATA
Figure 7-7 shows the internal register structure of the TMP100-Q1 and TMP101-Q1 devices. The 8-bit Pointer Register of the TMP100-Q1 and TMP101-Q1 devices is used to address a given data register. The Pointer Register uses the two LSBs to identify which of the data registers respond to a read or write command. Table 7-4 identifies the bits of the Pointer Register byte. Table 7-5 describes the pointer address of the registers available in the TMP100-Q1 and TMP101-Q1 devices. The power-up reset value of P1 and P0 is 00.