SBOS716D May   2015  – January 2020 TMP107

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital Temperature Output
      2. 7.3.2 Temperature Limits and Alert
        1. 7.3.2.1 ALERT1, ALERT2, R1, and R2 Pins
      3. 7.3.3 SMAART Wire™ Communication Interface
        1. 7.3.3.1 Communication Protocol
          1. 7.3.3.1.1 Calibration Phase
          2. 7.3.3.1.2 Command and Address Phase
            1. 7.3.3.1.2.1 Global or Individual (G/nI) Bit
            2. 7.3.3.1.2.2 Read/Write (R/nW) Bit
            3. 7.3.3.1.2.3 Command or Address (C/nA) Bit:
          3. 7.3.3.1.3 Register Pointer Phase
          4. 7.3.3.1.4 Data Phase
        2. 7.3.3.2 SMAART Wire™ Operations
          1. 7.3.3.2.1 Command Operations
            1. 7.3.3.2.1.1 Address Initialize
            2. 7.3.3.2.1.2 Last Device Poll
            3. 7.3.3.2.1.3 Global Software Reset
          2. 7.3.3.2.2 Address Operations
            1. 7.3.3.2.2.1 Individual Write
            2. 7.3.3.2.2.2 Individual Read
            3. 7.3.3.2.2.3 Global Write
            4. 7.3.3.2.2.4 Global Read
    4. 7.4 Device Functional Modes
      1. 7.4.1 Continuous-Conversion Mode
      2. 7.4.2 Shutdown Mode
      3. 7.4.3 One-Shot Mode
    5. 7.5 Programming
      1. 7.5.1 EEPROM
      2. 7.5.2 EEPROM Operations
        1. 7.5.2.1 EEPROM Unlock
        2. 7.5.2.2 EEPROM Lock
        3. 7.5.2.3 EEPROM Programming
        4. 7.5.2.4 EEPROM Acquire or Read
    6. 7.6 Register Map
      1. 7.6.1 Temperature Register (address = 0h) [reset = 0h]
        1. Table 4. Temperature Register Field Descriptions
      2. 7.6.2 Configuration Register (address = 1h) [reset = A000h]
        1. Table 5. Configuration Register Field Descriptions
      3. 7.6.3 High Limit 1 Register (address = 2h) [reset = 7FFCh]
        1. Table 7. High Limit 1 Register Field Descriptions
      4. 7.6.4 Low Limit 1 Register (address = 3h) [reset = 8000h]
        1. Table 8. Low Limit 1 Register Field Descriptions
      5. 7.6.5 High Limit 2 Register (address = 4h) [reset = 7FFCh]
        1. Table 9. High Limit 2 Register Field Descriptions
      6. 7.6.6 Low Limit 2 Register (address = 5h) [reset = 8000h]
        1. Table 10. Low Limit 2 Register Field Descriptions
      7. 7.6.7 EEPROM n Register (where n = 1 to 8) (addresses = 6h to Dh) [reset = 0h]
        1. Table 11. EEPROM Register bits
      8. 7.6.8 Die ID Register (address = Fh) [reset = 1107h]
        1. Table 12. Die ID Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Connecting Multiple Devices
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Voltage Drop Effect
          2. 8.2.1.2.2 EEPROM Programming Current
          3. 8.2.1.2.3 Power Savings
          4. 8.2.1.2.4 Accuracy
          5. 8.2.1.2.5 Electromagnetic Interference (EMI)
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Connecting ALERT1 and ALERT2 Pins
      3. 8.2.3 ALERT1 and ALERT2 Pins Used as General-Purpose Output (GPO)
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.2 Temperature Limits and Alert

The TMP107 has two ALERTx pins (ALERT1 and ALERT2) for under- and overtemperature monitor functions. Both pins have independent, dynamically-programmable limits. At the end of each conversion, the temperature result is compared with the high limit and low limit registers. If the temperature is outside the limit window, the respective ALERTx pin trips. There are two polarity bits that set the active state of the ALERTx pin. The TMP107 has two flag bits (FHx and FLx) for each alert condition to indicate in which direction the temperature has moved outside of the limit window.

There are two operating modes used for alerts and flags: therm and alert. In therm mode, the ALERTx pins and FHx and FLx flags are outputs of a transparent comparator. In alert mode, the ALERTx pins and FHx and FLx flags are latched interrupts. Select between alert mode or therm mode by using the Tx/Ax (T1/A1 and T2/A2) bits in the configuration register.

In alert mode (Tx/Ax = 0, default), the high and low limits form a temperature window. At the end of a conversion, if the temperature result exceeds the high limit or is less than the low limit, the respective flag (either FHx or FLx) and the ALERTx pin are asserted. If the alert outputs of multiple TMP107s are connected together, the TMP107 tripped alerts are still identifiable. To clear the ALERTx pin, issue a global alert clear x command, or read the configuration register as shown in Figure 16. To clear the FHx or FLx flag, read the configuration register. Alert-mode operation is shown in Figure 16.

TMP107 ai_alertresp_sbos716.gifFigure 16. ALERTx Pin Behavior in Alert Mode (POLx = 0)

In therm mode (Tx/Ax = 1), the high and low limits are used to form an upper-limit threshold detector. If the temperature result exceeds the high limit, the FHx flag and the ALERTx pin are asserted. The FHx flag and the ALERTx pin are then deasserted only after the temperature falls below the low limit. In therm mode, only the FHx flag is active. The FLx flag always reads 0. In therm mode, ALERTx and the flags are asserted and deasserted only at the end of a conversion and cannot be cleared by a configuration register read or global alert clear x command. Figure 17 shows therm-mode operation.

TMP107 ai_thermresp_sbos716.gifFigure 17. ALERTx Pin Behavior in Therm Mode (POLx = 0)

The limit registers default values are programmed in the EEPROM, and are acquired during power up or reset. The values can be dynamically changed by writing to the register. Disable alert and flag functionality by programming the high limit register to the highest temperature (7FFCh) and the low limit register to the lowest temperature (8000h). When disabled, the alert pins can still be controlled by polarity bits POL1 and POL2 (bit 7 and bit 3, respectively, in the configuration register) so that they work like general-purpose outputs (GPOs).