SBOS854F March   2018  – June 2024 TMP1075

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics:TMP1075
    6. 6.6  Electrical Characteristics: TMP1075N
    7. 6.7  Timing Requirements:TMP1075
    8. 6.8  Timing Requirements: TMP1075N
    9. 6.9  Switching Characteristics
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital Temperature Output
      2. 7.3.2 I2C and SMBus Serial Interface
        1. 7.3.2.1  Bus Overview
        2. 7.3.2.2  Serial Bus Address
        3. 7.3.2.3  Pointer Register
          1. 7.3.2.3.1 Pointer Register Byte [reset = 00h]
        4. 7.3.2.4  Writing and Reading to the TMP1075
        5. 7.3.2.5  Operation Mode
          1. 7.3.2.5.1 Receiver Mode
          2. 7.3.2.5.2 Transmitter Mode
        6. 7.3.2.6  SMBus Alert Function
        7. 7.3.2.7  General Call- Reset Function
        8. 7.3.2.8  High-Speed Mode (HS)
        9. 7.3.2.9  Coexists in I3C Mixed Fast Mode
        10. 7.3.2.10 Time-Out Function
      3. 7.3.3 Timing Diagrams
      4. 7.3.4 Two-Wire Timing Diagrams
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode (SD)
      2. 7.4.2 One-Shot Mode (OS)
      3. 7.4.3 Continuous Conversion Mode (CC)
      4. 7.4.4 Thermostat Mode (TM)
        1. 7.4.4.1 Comparator Mode (TM = 0)
        2. 7.4.4.2 Interrupt Mode (TM = 1)
        3. 7.4.4.3 Polarity Mode (POL)
    5. 7.5 Register Map
      1. 7.5.1 Register Descriptions
        1. 7.5.1.1 Temperature Register (address = 00h) [default reset = 0000h]
        2. 7.5.1.2 Configuration Register (address = 01h) [default reset = 00FFh (60A0h TMP1075N)]
        3. 7.5.1.3 Low Limit Register (address = 02h) [default reset = 4B00h]
        4. 7.5.1.4 High Limit Register (address = 03h) [default reset = 5000h]
        5. 7.5.1.5 Device ID Register (address = 0Fh) [default reset = 7500]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Migrating From the xx75 Device Family
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.4.2 Interrupt Mode (TM = 1)

In interrupt mode (TM = 1), the device starts to compare temperature readings with the high limit register value. The ALERT pin becomes active when the temperature equals or exceeds THIGH for a consecutive number of conversions as set by the Fault Queue bits [F1:F0]. The ALERT pin remains active until the pin is cleared by one of three events: a read of any register, a successful SMBus Alert response, or a shutdown command. After the ALERT pin is cleared, the device starts to compare temperature readings with the TLOW. The ALERT pin becomes active again only when the temperature drops below TLOW for a consecutive number of conversions as set by the Fault Queue bits. The ALERT pin remains active until cleared by any of the same three clearing events. After the ALERT pin is cleared by one of the events, the cycle repeats and the device resumes to compare the temperature to THIGH. The interrupt mode history is cleared by a change in the TM=0 bit, setting the device to SD mode, or resetting the device on the TMP1075 non-N orderables.