SNIS217C december   2020  – may 2023 TMP139

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power-Up Sequence
      2. 7.3.2 Power-Down and Device Reset
      3. 7.3.3 Temperature Result and Limits
      4. 7.3.4 Bus Reset
      5. 7.3.5 Interrupt Generation
      6. 7.3.6 Parity Error Check
      7. 7.3.7 Packet Error Check
    4. 7.4 Device Functional Modes
      1. 7.4.1 Conversion Mode
      2. 7.4.2 Serial Address
      3. 7.4.3 I2C Mode Operation
        1. 7.4.3.1 Host I2C Write Operation
        2. 7.4.3.2 Host I2C Read Operation
        3. 7.4.3.3 Host I2C Read Operation in Default Read Address Pointer Mode
        4. 7.4.3.4 Switching from I2C Mode to I3C Basic Mode
      4. 7.4.4 I3C Basic Mode Operation
        1. 7.4.4.1 Host I3C Write Operation without PEC
        2. 7.4.4.2 Host I3C Write Operation with PEC
        3. 7.4.4.3 Host I3C Read Operation without PEC
        4. 7.4.4.4 Host I3C Read Operation with PEC
        5. 7.4.4.5 Host I3C Read Operation in Default Read Address Pointer Mode
      5. 7.4.5 In Band Interrupt
        1. 7.4.5.1 In Band Interrupt Arbitration Rules
        2. 7.4.5.2 In Band Interrupt Bus Transaction
      6. 7.4.6 Common Command Codes Support
        1. 7.4.6.1 ENEC CCC
        2. 7.4.6.2 DISEC CCC
        3. 7.4.6.3 RSTDAA CCC
        4. 7.4.6.4 SETAASA CCC
        5. 7.4.6.5 GETSTATUS CCC
        6. 7.4.6.6 DEVCAP CCC
        7. 7.4.6.7 SETHID CCC
        8. 7.4.6.8 DEVCTRL CCC
      7. 7.4.7 I/O Operation
      8. 7.4.8 Timing Diagrams
    5. 7.5 Programming
      1. 7.5.1 Enabling Interrupt Mechanism
      2. 7.5.2 Clearing Interrupt
    6. 7.6 Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YAH|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.5.1 In Band Interrupt Arbitration Rules

Based on the state of the host controller readiness and due to the fact that there are multiple devices on the bus, the IBI generation and arbitration must follow some rules, as described below. All of these conditions assume that the bus has been inactive for tAVAL period.

  1. When the host controller starts a write or read with IBI header, TMP139 shall start driving its own address on the bus. The host on seeing a value other than the IBI header shall no longer drive the SDA, allowing the TMP139 to transmit its device header along with R/W bit set to 1.
  2. If the host controller can accept the IBI from the device, it shall ACK the device address, release the bus on the falling edge of SCL and shall accept the bytes sent by the TMP139.
  3. If the host controller cannot accept the IBI from the device, it shall NACK the device address and issue a Stop condition on the bus. The TMP139 shall retry another IBI only after tAVAL period.
  4. When the host controller starts a write or read without an IBI header to a device on the bus which has a lower device address than the TMP139, the device on detecting a mismatch, shall no longer participate on the bus and retry another IBI only after tAVAL period.
  5. When the host controller starts a write or read without an IBI header to a device on the bus which has a higher device address than the TMP139, the device wins the bus arbitration and the host shall no longer participate on the bus. The host may accept the IBI by sending an ACK or disregard the IBI by sending a NACK. In the latter case, TMP139 shall retry another IBI only after tAVAL period.
  6. When the host controller starts a write or read transaction without an IBI header to the TMP139 which is also requesting an IBI, either the host or TMP139 can win.
  7. If the host controller starts a write transaction, then it shall win the bus arbitration and the TMP139 shall let go of the bus. The TMP139 shall retry another IBI only after tAVAL period.
  8. If the host controller starts a read transaction, then all the bits shall match. However at this point the host is expecting an ACK from the TMP139 for the read request, while the TMP139 is waiting for an ACK from the host for the IBI. As a result there shall be a NACK on the bus. In such a case, the TMP139 shall retry the IBI only after tAVAL period. However if the host issues start (or Repeated Start) and attempts the read transaction before the tAVAL period, it shall get an ACK from the TMP139 and the host read shall win the arbitration on the bus.
  9. As described above, in the case when there are multiple devices initiating an IBI at the same time, the device which has the lowest device address shall win the bus arbitration and the TMP139 when it detects a loss on the bus arbitration, shall retry another IBI only after tAVAL period