SNIS217C december   2020  – may 2023 TMP139

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power-Up Sequence
      2. 7.3.2 Power-Down and Device Reset
      3. 7.3.3 Temperature Result and Limits
      4. 7.3.4 Bus Reset
      5. 7.3.5 Interrupt Generation
      6. 7.3.6 Parity Error Check
      7. 7.3.7 Packet Error Check
    4. 7.4 Device Functional Modes
      1. 7.4.1 Conversion Mode
      2. 7.4.2 Serial Address
      3. 7.4.3 I2C Mode Operation
        1. 7.4.3.1 Host I2C Write Operation
        2. 7.4.3.2 Host I2C Read Operation
        3. 7.4.3.3 Host I2C Read Operation in Default Read Address Pointer Mode
        4. 7.4.3.4 Switching from I2C Mode to I3C Basic Mode
      4. 7.4.4 I3C Basic Mode Operation
        1. 7.4.4.1 Host I3C Write Operation without PEC
        2. 7.4.4.2 Host I3C Write Operation with PEC
        3. 7.4.4.3 Host I3C Read Operation without PEC
        4. 7.4.4.4 Host I3C Read Operation with PEC
        5. 7.4.4.5 Host I3C Read Operation in Default Read Address Pointer Mode
      5. 7.4.5 In Band Interrupt
        1. 7.4.5.1 In Band Interrupt Arbitration Rules
        2. 7.4.5.2 In Band Interrupt Bus Transaction
      6. 7.4.6 Common Command Codes Support
        1. 7.4.6.1 ENEC CCC
        2. 7.4.6.2 DISEC CCC
        3. 7.4.6.3 RSTDAA CCC
        4. 7.4.6.4 SETAASA CCC
        5. 7.4.6.5 GETSTATUS CCC
        6. 7.4.6.6 DEVCAP CCC
        7. 7.4.6.7 SETHID CCC
        8. 7.4.6.8 DEVCTRL CCC
      7. 7.4.7 I/O Operation
      8. 7.4.8 Timing Diagrams
    5. 7.5 Programming
      1. 7.5.1 Enabling Interrupt Mechanism
      2. 7.5.2 Clearing Interrupt
    6. 7.6 Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YAH|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.4.3 Host I3C Read Operation without PEC

As shown in Figure 7-15 and Figure 7-16, an I3C basic mode read is same as I2C read operation. For all bytes sent by the device, the 9th bit is the T-bit, which is used by the device and host to negotiate continuation of the read transfer. During the read phase, the device drives the T-bit as 1, before the rising edge to tell the host that it can send more bytes or drives the T-bit as 0, to indicate to the host that the device wants to terminate the transfer and the host shall respond with either a Stop or Repeated Start on the bus. The host may also terminate the transfer by driving the T-bit as 0, only when device sends the T-bit as 1, which creates a repeated start condition on the bus. Additionally, the host may send a Stop on the bus. When the IBI is enabled by the host, it must send the IBI header byte which consists of 7'h7E+R/W = 0, before it sends the device address. This allows the participating devices on the bus, to arbitrate between themselves if more than one device has an interrupt condition that needs to be communicated to the host.

GUID-9E8EF20D-FE72-4AA5-9B9C-40A0C87A1E1C-low.gifFigure 7-15 I3C Basic Mode Read
GUID-BCC6F327-A538-4015-A8FC-F6C38A2B8FFF-low.gifFigure 7-16 I3C Basic Mode Read with IBI Header

The TMP139 shall NACK the read phase of the transaction if there was a parity error in the write phase before the repeated start. The device shall also send the T-bit as 0, if the host attempts to read data continuously such that the internal read address pointer reaches 255, which is the last register in the register map table. Additionally, if the host attempts to start a new transaction with a Repeated Start to the same device, when there was a parity error in the previous transaction, then TMP139 shall NACK the device address to indicate an error condition to the host. The host must first clear the parity error condition before performing any new transfer to the TMP139. When IBI is enabled, the device can communicate to the host the error conditions seen, using IBI. However when IBI is not enabled, it is strongly recommended that the host check the error status register to ensure that no parity error was detected on the bus.