SNIS217C december   2020  – may 2023 TMP139

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power-Up Sequence
      2. 7.3.2 Power-Down and Device Reset
      3. 7.3.3 Temperature Result and Limits
      4. 7.3.4 Bus Reset
      5. 7.3.5 Interrupt Generation
      6. 7.3.6 Parity Error Check
      7. 7.3.7 Packet Error Check
    4. 7.4 Device Functional Modes
      1. 7.4.1 Conversion Mode
      2. 7.4.2 Serial Address
      3. 7.4.3 I2C Mode Operation
        1. 7.4.3.1 Host I2C Write Operation
        2. 7.4.3.2 Host I2C Read Operation
        3. 7.4.3.3 Host I2C Read Operation in Default Read Address Pointer Mode
        4. 7.4.3.4 Switching from I2C Mode to I3C Basic Mode
      4. 7.4.4 I3C Basic Mode Operation
        1. 7.4.4.1 Host I3C Write Operation without PEC
        2. 7.4.4.2 Host I3C Write Operation with PEC
        3. 7.4.4.3 Host I3C Read Operation without PEC
        4. 7.4.4.4 Host I3C Read Operation with PEC
        5. 7.4.4.5 Host I3C Read Operation in Default Read Address Pointer Mode
      5. 7.4.5 In Band Interrupt
        1. 7.4.5.1 In Band Interrupt Arbitration Rules
        2. 7.4.5.2 In Band Interrupt Bus Transaction
      6. 7.4.6 Common Command Codes Support
        1. 7.4.6.1 ENEC CCC
        2. 7.4.6.2 DISEC CCC
        3. 7.4.6.3 RSTDAA CCC
        4. 7.4.6.4 SETAASA CCC
        5. 7.4.6.5 GETSTATUS CCC
        6. 7.4.6.6 DEVCAP CCC
        7. 7.4.6.7 SETHID CCC
        8. 7.4.6.8 DEVCTRL CCC
      7. 7.4.7 I/O Operation
      8. 7.4.8 Timing Diagrams
    5. 7.5 Programming
      1. 7.5.1 Enabling Interrupt Mechanism
      2. 7.5.2 Clearing Interrupt
    6. 7.6 Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YAH|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.4.4 Host I3C Read Operation with PEC

As shown in Figure 7-17 and Figure 7-18, when the PEC is enabled by the host, an additional byte is added by the host after sending the register address. The format for the additional byte is described in Table 7-5. Since only one and two byte reads are permitted by the CMD byte, the device shall terminate the read phase after sending one byte of data and PEC byte or two byte of data and PEC byte, followed by the T-bit as 0. In an unlikely case where the host sets the register address as 255, and attempts a read of two bytes, the device result is not guaranteed.

GUID-39ABD6C0-863E-4E1D-B7B8-6E590DA06851-low.gifFigure 7-17 I3C Basic Mode Read with PEC enabled
GUID-11B6680C-B1F5-4182-A2AD-DC1AA3FAFABF-low.gifFigure 7-18 I3C Basic Mode Read with PEC enabled and IBI Header

If the CMD value sent by the host is not valid for TMP139, the device shall NACK the read phase.

The TMP139 shall NACK the read phase of the transaction if there was a parity error in the write phase before the Repeated Start. If the host attempts to start a new transaction with a Repeated Start to the same device, then TMP139 shall NACK the device address to indicate an error condition to the host. The host must first clear the parity error condition before performing any new transfer to the TMP139.

If there is a PEC error, then the TMP139 shall NACK the read phase of the transaction. If the host attempts to start a new transaction with a Repeated Start to the same device, then TMP139 shall NACK the device address to indicate an existing error condition to the host. The host must first clear the PEC error condition before performing any new transfer to the TMP139.

When IBI is enabled, the device can communicate to the host the error conditions seen, using IBI. However when IBI is not enabled, it is strongly recommended that the host check the error status register to ensure that no parity or PEC error was detected on the bus.