SBOSA45C february 2022 – may 2023 TMP1826
PRODUCTION DATA
The bus reset phase is the beginning of the communication. The phase is initiated by the host by holding the 1-Wire data line low for a period tRSTL. All devices on the bus, irrespective of their current state shall respond to the bus reset, by reinitializing their internal state and responding to the host initiated bus reset. The devices respond after a minimum of tPDH, by holding the 1-Wire low for a time period of tRSTH as shown in Figure 8-1.
All devices when powered up are configured with the OD_EN bit set as '1' in the device configuration-2 and OD flag set as '1' in status register. If the host sends a bus reset pulse of 48 µs to 80 µs, then only devices operating in overdrive speed shall respond to the bus reset pulse, while devices operating in standard mode shall continue to wait for a standard mode bus reset.
If the host sends a bus reset pulse of minimum tRSTL for standard mode, the device shall reset the OD_EN bit to '0' and respond to the bus reset in standard mode. If the bus consists of mixed standard and overdrive speed devices, then sending a bus reset pulse in standard mode shall reset all devices to standard mode speed of operation.
It is illegal for the host to send the bus reset for a particular speed of operation and then communicate at the other speed mode. Also, if a bus reset pulse is sent which is greater than 80 µs (but less than 480 µs), then the device communication shall be reset, though the device operation is not ensured.