SBOSA45C february   2022  – may 2023 TMP1826

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (cont.)
  7. 6 Device Comparison
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 1-Wire Interface Timing
    7. 8.7 EEPROM Characteristics
    8. 8.8 Timing Diagrams
    9. 8.9 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power Up
      2. 9.3.2  Power Mode Switch
      3. 9.3.3  Bus Pullup Resistor
      4. 9.3.4  Temperature Results
      5. 9.3.5  Temperature Offset
      6. 9.3.6  Temperature Alert
      7. 9.3.7  Standard Device Address
        1. 9.3.7.1 Unique 64-Bit Device Address and ID
      8. 9.3.8  Flexible Device Address
        1. 9.3.8.1 Non-Volatile Short Address
        2. 9.3.8.2 IO Hardware Address
        3. 9.3.8.3 Resistor Address
        4. 9.3.8.4 Combined IO and Resistor Address
      9. 9.3.9  CRC Generation
      10. 9.3.10 Functional Register Map
      11. 9.3.11 User Memory Map
      12. 9.3.12 Bit Communication
        1. 9.3.12.1 Host Write, Device Read
        2. 9.3.12.2 Host Read, Device Write
      13. 9.3.13 Bus Speed
      14. 9.3.14 NIST Traceability
    4. 9.4 Device Functional Modes
      1. 9.4.1 Conversion Modes
        1. 9.4.1.1 Basic One-Shot Conversion Mode
        2. 9.4.1.2 Auto Conversion Mode
        3. 9.4.1.3 Stacked Conversion Mode
        4. 9.4.1.4 Continuous Conversion Mode
      2. 9.4.2 Alert Function
        1. 9.4.2.1 Alert Mode
        2. 9.4.2.2 Comparator Mode
      3. 9.4.3 1-Wire Interface Communication
        1. 9.4.3.1 Bus Reset Phase
        2. 9.4.3.2 Address Phase
          1. 9.4.3.2.1 READADDR (33h)
          2. 9.4.3.2.2 MATCHADDR (55h)
          3. 9.4.3.2.3 SEARCHADDR (F0h)
          4. 9.4.3.2.4 ALERTSEARCH (ECh)
          5. 9.4.3.2.5 SKIPADDR (CCh)
          6. 9.4.3.2.6 OVD SKIPADDR (3Ch)
          7. 9.4.3.2.7 OVD MATCHADDR (69h)
          8. 9.4.3.2.8 FLEXADDR (0Fh)
        3. 9.4.3.3 Function Phase
          1. 9.4.3.3.1  CONVERTTEMP (44h)
          2. 9.4.3.3.2  WRITE SCRATCHPAD-1 (4Eh)
          3. 9.4.3.3.3  READ SCRATCHPAD-1 (BEh)
          4. 9.4.3.3.4  COPY SCRATCHPAD-1 (48h)
          5. 9.4.3.3.5  WRITE SCRATCHPAD-2 (0Fh)
          6. 9.4.3.3.6  READ SCRATCHPAD-2 (AAh)
          7. 9.4.3.3.7  COPY SCRATCHPAD-2 (55h)
          8. 9.4.3.3.8  READ EEPROM (F0h)
          9. 9.4.3.3.9  GPIO WRITE (A5h)
          10. 9.4.3.3.10 GPIO READ (F5h)
      4. 9.4.4 NVM Operations
        1. 9.4.4.1 Programming User Data
        2. 9.4.4.2 Register and Memory Protection
          1. 9.4.4.2.1 Scratchpad-1 Register Protection
          2. 9.4.4.2.2 User Memory Protection
    5. 9.5 Programming
      1. 9.5.1 Single Device Temperature Conversion and Read
      2. 9.5.2 Multiple Device Temperature Conversion and Read
      3. 9.5.3 Register Scratchpad-1 Update and Commit
      4. 9.5.4 Single Device EEPROM Programming and Verify
      5. 9.5.5 Single Device EEPROM Page Lock Operation
      6. 9.5.6 Multiple Device IO Read
      7. 9.5.7 Multiple Device IO Write
    6. 9.6 Register Map
      1. 9.6.1  Temperature Result LSB Register (Scratchpad-1 offset = 00h) [reset = 00h]
      2. 9.6.2  Temperature Result MSB Register (Scratchpad-1 offset = 01h) [reset = 00h]
      3. 9.6.3  Status Register (Scratchpad-1 offset = 02h) [reset = 3Ch]
      4. 9.6.4  Device Configuration-1 Register (Scratchpad-1 offset = 04h) [reset = 70h]
      5. 9.6.5  Device Configuration-2 Register (Scratchpad-1 offset = 05h) [reset = 80h]
      6. 9.6.6  Short Address Register (Scratchpad-1 offset = 06h) [reset = 00h]
      7. 9.6.7  Temperature Alert Low LSB Register (Scratchpad-1 offset = 08h) [reset = 00h]
      8. 9.6.8  Temperature Alert Low MSB Register (Scratchpad-1 offset = 09h) [reset = 00h]
      9. 9.6.9  Temperature Alert High LSB Register (Scratchpad-1 offset = 0Ah) [reset = F0h]
      10. 9.6.10 Temperature Alert High MSB Register (Scratchpad-1 offset = 0Bh) [reset = 07h]
      11. 9.6.11 Temperature Offset LSB Register (Scratchpad-1 offset = 0Ch) [reset = 00h]
      12. 9.6.12 Temperature Offset MSB Register (Scratchpad-1 offset = 0Dh) [reset = 00h]
      13. 9.6.13 IO Read Register [reset = F0h]
      14. 9.6.14 IO Configuration Register [reset = 00h]
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Bus Powered Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
      2. 10.2.2 Supply Powered Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
      3. 10.2.3 UART Interface for Communication
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.6.13 IO Read Register [reset = F0h]

The register is used to read the state of the IO0 to IO3 pin. The register values are updated when the GPIO READ function is issued by the host. When IO2 is configured to function as an alert pin, it provides a status of the alert pin.

Return to Register Map.

Figure 9-36 IO Read Register
7 6 5 4 3 2 1 0
nIO3_STATE nIO2_STATE nIO1_STATE nIO0_STATE IO3_STATE IO2_STATE IO1_STATE IO0_STATE
R-1b R-1b R-1b R-1b R-0b R-0b R-0b R-0b
Table 9-28 IO Read Register Field Descriptions
Bit Field Type Reset Description
7 nIO3_STATE R 1b Read inverted value of the IO3 pin when configured as a digital input or output
6 nIO2_STATE R 1b Read inverted value of the IO2 pin when configured as a digital input or output
5 nIO1_STATE R 1b Read inverted value of the IO1 pin when configured as a digital input or output
4 nIO0_STATE R 1b Read inverted value of the IO0 pin when configured as a digital input or output
3 IO3_STATE R 0b Read value of the IO3 pin when configured as a digital input or output
2 IO2_STATE R 0b Read value of the IO2 pin when configured as a digital input or output
1 IO1_STATE R 0b Read value of the IO1 pin when configured as a digital input or output
0 IO0_STATE R 0b Read value of the IO0 pin when configured as a digital input or output