SBOSA45D February 2022 – January 2025 TMP1826
PRODUCTION DATA
The 1-Wire® interface communication does not have a reference clock, therefore all communication is performed asynchronously with fixed time slot (tSLOT) and variable pulse width to indicate logic '0' and '1'. In idle state, the external pullup resistor holds the line high. All bit communication, whether the communication is a write or a read, are initiated by the host by driving the data line low to generate a falling edge and the bit value is decoded as the time for which the data line is held low or high after the falling edge.
Even though the communication is one bit at a time, the data exchanged between the host and device is performed at byte boundary. Every byte is sent least significant bit first. The device behavior is not ensured when incomplete bytes are sent.