SPRS867 Data sheet

SPRS867A February 2013 – August 2016 TMS320DM369

PRODUCTION DATA.

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

ZCE|338

Thermal pad, mechanical data (Package|Pins)

Orderable Information

sprs867a_oa

7 Peripheral Information and Electrical Specifications

7.1 Parameter Information Device-Specific Information

A. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A model of the tester pin electronics is shown in Figure 7-1. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin and the input signals are driven between 0V and the appropriate I/O supply for the signal.

Figure 7-1 Test Load Circuit for AC Timing Measurements

The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving.

7.1.1 Signal Transition Levels

All input and output timing parameters are referenced to V_ref for both "0" and "1" logic levels. For 3.3 V I/O, V_ref = 1.65 V. For 1.8 V I/O, V_ref = 0.9 V.

Figure 7-2 Input and Output Voltage Reference Levels for AC Timing Measurements

All rise and fall transition timing parameters are referenced to V_IL MAX and V_IH MIN for input clocks, V_OLMAX and V_OH MIN for output clocks.

Figure 7-3 Rise and Fall Transition Time Voltage Reference Levels

7.1.2 Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis Application Report (SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing differences.

7.2 Recommended Clock and Control Signal Transition Behavior

All clocks and control signals should transition between V_IH and V_IL (or between V_IL and V_IH) in a monotonic manner.

7.3 Power Supplies

The power supplies are summarized in Table 7-1.

Table 7-1 Power Supplies

CUSTOMER BOARD SUPPLY	TOLERANCE	PACKAGE PLANE	DEVICE PLANE	DESCRIPTION
1.35V	±5%	1.35V	CV_DD	Core power supply
			V_{DD12_PRTCSS}	RTC oscillator power supply
				PWR CTRL power supply
				PWR CTRL 1.35-V I/O power supply
			V_{DDA12_DAC}	DAC 1.35-V analog power supply
			V_PP	V_PP power supply
1.8 V	±5%	1.8 V	V_{DD18_PRTCSS}	PWR CTRL 1.8-V power supply
			V_DDMXI	MXI1 (oscillator) 1.8-V power supply
			V_{DD18_SLDO}	Power supply for internal RAM For proper device operation, this pin must be connected to V_DDS18.
			V_{DD18_DDR}	1.8-V DDR2 Supply Voltage
			V_{DDA18_PLL}	1.8-V PLL Analog Supply Voltage
			V_{DDA18_USB}	1.8-V USB Analog Supply Voltage
			V_{DDA18_VC}	1.8-V Voice Codec Module Analog Supply Voltage
			V_{DDA18_DAC}	1.8-V DAC Analog Supply Voltage
			V_DDS18	1.8-V Supply Voltage
			V_{DDA18_ADC}	1.8-V ADC Supply Voltage
3.3 V	±5%	3.3 V	V_DDS33	3.3-V I/O Supply Voltage
			V_{DDA33_USB}	3.3-V USB Analog Supply Voltage
			V_{DDA33_VC}	3.3-V Voice Codec Module Analog Supply Voltage
1.8/3.3 V	±5%	1.8/3.3 V	V_{DD_AEMIF1_18_33}	Switchable 3.3/1.8-V EMIF1 Supply Voltage ⁽¹⁾ Note: Power supply is switchable for AEMIF and its multiplexed peripherals (3.3/1.8 V) ⁽³⁾.
			V_{DD_AEMIF2_18_33}	Switchable 3.3/1.8-V EMIF2 Supply Voltage ⁽²⁾ Note: Power supply is switchable for AEMIF and its multiplexed peripherals (3.3/1.8 V) ⁽³⁾.
			V_{DD_ISIF18_33}	Switchable 3.3/1.8-V ISIF Supply Voltage ⁽⁴⁾ Note: Power supply is switchable for ISIF and its multiplexed peripherals (3.3V/1.8V)⁽⁵⁾
0 V		0 V	V_{SS_MX1}	Oscillator (MXI1) ground Note: For proper device operation, connect to external crystal capacitor ground and must be kept separate from other grounds.
0 V		0 V	V_{SS_32K}	Oscillator (32K) ground Note: For proper device operation, connect to external crystal capacitor ground and must be kept separate from other grounds.
0 V		0 V	V_SS	Ground
0 V		0 V	V_SSA	PLL ground Note: For proper device operation, keep separate from digital ground V_SS.
0 V		0 V	V_{SSA18_USB}	USB ground
0 V		0 V	V_{SSA33_USB}	3.3-V USB ground
0 V		0 V	V_{SSA33_VC}	3.3-V Voice Codec Module ground
0 V		0 V	V_{SSA18_VC}	1.8-V Voice Codec Module ground
0 V		0 V	V_{SSA_ADC}	Analog-to-digital converter (ADC) ground
0 V		0 V	V_{SSA18_DAC}	1.8-V DAC ground
0 V		0 V	V_{SSA12_DAC}	1.2-V DAC ground
V_{DD18_DDR}*0.5		V_{DD18_DDR}*0.5	DDR_VREF	DRR reference voltage (V_DDS divided by 2, through board resistors)
0.5V	±5%		V_REF	DAC reference voltage
5.25V			USB_VBUS	VBUS

(1) V_{DD_AEMIF1_18_33} : can be used as a power supply for EM_A[3:13], EM_BA0, EM_BA1, EM_CE[0], EM_ADV, EM_CLK, EM_D[8:15 ]pins, Keyscan, or GPIO pins.

(2) V_{DD_AEMIF2_18_33:}can be used as a power supply for EM_A[0:2], EM_CE[1], EM_WE, EM_OE, EM_WAIT, EM_D[0:7] pins, HPI, Keyscan, or GPIO pins.

(3) Example 1: V_{DD_AEMIF2_18_33} at 1.8-V for 8-bit NAND V_{DD_AEMIF1_18_33} at 3.3-V for GPIO.
Example 2: V_{DD_AEMIF1_18_33} and V_{DD_AEMIF2_18_33} at 1.8-V for 16-bit NAND.

(4) V_{DD_ISIF_18_33}: can be used as a power supply for VPFE pins (CIN[7:0], YIN[7:0], C_WE_FIELD, PCLK), or SPI3 (SPI3_SCLK,SPI3_SIMO,SPI3_SCS[0], SPI3_SCS[1]) or USBDRVVBUS or GPIO pins.

(5) Example 1 V_{DD_ISIF_18_33} power supply can be at 1.8V for VPFE pin functionality or it can be at 3.3V if other peripherals pin functionality is to be used like SPI3 or GPIO or CLKOUT0, or USBDRVVBUS.

7.4 Power-Supply Sequencing

In order to ensure device reliability, the device requires the following power supply power-on and power-off sequences. See Table 6-2, Recommended Operating Conditions, for a description of the power supplies.

The following power sequences are recommended to prevent damage to the device.
The PRTCSS core must always be powered-on and powered-off regardless of whether the PRTCSS feature is used.
If the PRTCSS sequencer is to be used in any PRTCSS modes, please see the TMS320DM36x PRTCSS User's Guide (SPRUFJ0) for more details on the differences to the power sequence.

7.4.1 Simple Power-On and Power-Off Method

The following steps must be followed in sequential order for the simple power-on method:

Power on the PRTCSS/ Main core (1.35 V).
Power on the PRTCSS/Main I/O (1.8 V).
Power on the Main/Analog I/O (3.3 V).

Note for simple power-on: RESET must be low until all supplies are ramped up.

The following steps should be followed for the simple power-off method:

Power off the Main/Analog I/O (3.3 V).
Power off the PRTCSS/Main I/O (1.8 V).
Power off the PRTCSS/Main core (1.35 V).

Notes for simple power-off:

If RESET is low, steps 2 and 3 may be performed simultaneously.
If RESET is not low, these steps must be followed sequentially.

7.4.2 Restricted Power-On and Power-Off Method

The following steps should be followed for the restricted power-on method:

Power on the PRTCSS/ Main core (1.35 V).
Power on the PRTCSS/Main I/O (1.8 V).
Power on the Main/Analog I/O (3.3 V).

Notes for restricted power-on:

RESET must be low until all supplies are ramped up.
Steps 1, 2, and 3 may be performed simultaneously if the Main core finishes ramping up before the I/Os and the maximum delta voltage difference between the 1.8- and 3.3-V I/Os is 2.0 V until the 1.8-V I/O reaches the full voltage.

The following steps should be followed for the restricted power-off method:

Power off Main/Analog I/O (3.3 V).
Power off PRTCSS/Main I/O (1.8 V).
Power off PRTCSS/Main core (1.35 V).

Notes for restricted power-off:

The 3.3- and1.8-V I/Os may be powered off simultaneously if the maximum delta voltage difference between them is 2.0 V until the 1.8-V I/O is completely powered off, and the PRTCSS/Main core must be powered down last.

When booting the DM369 from OneNAND, you must ensure that the OneNAND device is ready with valid program instructions before the DM369 attempts to read program instructions from it. In particular, before you release the device's reset, you must allow time for OneNAND device power to stabilize and for the OneNAND device to complete its internal copy routine. During the internal copy routine, the OneNAND device copies boot code from its internal non-volatile memory to its internal boot memory section. Board designers typically achieve this requirement by design of the system power and reset supervisor circuit. See your OneNAND device datasheet for OneNAND power ramp and stabilization times and for OneNAND boot copy times.

7.4.3 Power-Supply Design Considerations

Core and I/O supply voltage regulators should be located close to the device to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications utilizing the device, the PC board should include separate power planes for core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.

7.4.4 Power-Supply Decoupling

In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close to the device. These caps need to be close to the power pins, no more than 1.25 cm maximum distance to be effective. Physically smaller caps, such as 0402, are better because of their lower parasitic inductance. Proper capacitance values are also important. Small bypass caps (near 560 pF) should be closest to the power pins. Medium bypass caps (220 nF or as large as can be obtained in a small package) should be next closest. TI recommends no less than 8 small and 8 medium caps per supply be placed immediately next to the BGA vias, using the "interior" BGA space and at least the corners of the "exterior".

Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order of 100 uF) should be furthest away, but still as close as possible. Large caps for each supply should be placed outside of the BGA footprint.

Any cap selection needs to be evaluated from a yield/manufacturing point-of-view. As with the selection of any component, verification of capacitor availability over the product’s production lifetime should be considered. See also Section 7.6.1 for additional recommendations on power supplies for the oscillator/PLL supplies.

7.5 Reset

7.5.1 Reset Electrical Data/Timing

Table 7-2 Timing Requirements for Reset ⁽¹⁾ ⁽²⁾ ⁽³⁾ (see Figure 7-4)

NO.			DEVICE		UNIT
NO.			MIN	MAX	UNIT
1	t_w(RESET)	Active low width of the RESET pulse	12C		ns
2	t_su(BOOT)	Setup time, boot configuration pins valid before RESET rising edge	2E		ns
3	t_h(BOOT)	Hold time, boot configuration pins valid after RESET rising edge	0		ns

(1) BTSEL[2:0] and AECFG[2:0] are the boot configuration pins during device reset.

(2) C = MXI1/CLKIN cycle time in ns. For example, when MXI1/CLKIN frequency is 24 MHz use C = 41.6 ns.

(3) E = 1/PLLC1SYSCLK4 cycle time in ns.

Figure 7-4 Reset Timing

7.6 Oscillators and Clocks

The device has one oscillator input/output pair (MXI1/MXO1) usable with external crystals or ceramic resonators to provide clock inputs. The optimal frequencies for the crystals are 19.2 MHz, 24 MHz, 27 MHz, and 36 MHz. Optionally, the oscillator inputs are configurable for use with external clock oscillators. If external clock oscillators are used, to minimize the clock jitter, a single clean power supply should power both the device and the external oscillator circuit and the minimum CLKIN rise and fall times must be observed. The electrical requirements and characteristics are described in this section.

The timing parameters for CLKOUT[2:0] are also described in this section. The device has three output clock pins (CLKOUT[2:0]). See Section 4.3 for more information on CLKOUT[2:0].

Note: Please ensure that the appropriate oscillator input pin (GIO81/OSCCFG) frequency range setting is set correctly. For more details on this pin setting, see Section 4.7.6.

7.6.1 MXI1 Oscillator

The MXI1 (typically 24 MHz, can also be 19.2 MHz, 27 MHz, or 36 MHz) oscillator provides the primary reference clock for the device. The on-chip oscillator requires an external crystal connected across the MXI1 and MXO1 pins, along with two load capacitors, as shown in Figure 7-5. The external crystal load capacitors must be connected only to the oscillator ground pin (V_{SS_MX1}). Do not connect to board ground (V_SS). Also, the PLL power pin (V_{DDA_PLL1}) should be connected to the power supply through a ferrite bead, L1 in the example circuit shown in Figure 7-5.

Note: If an external oscillator is to be used, the external oscillator clock signal should be connected to the MXI1 pin with a 1.8V amplitude. The MXO1 should be left unconnected and the VSS_MX1 signal should be connected to board ground (V_ss).

Figure 7-5 MXI1 Oscillator

The load capacitors, C1 and C2, should be chosen such that the equation is satisfied (typical values are C1 = C2 = 10 pF to 20 pF). CL in the equation is the load specified by the crystal manufacturer. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator pins (MXI1 and MXO1) and to the V_{SS_MX1} pin.

Table 7-3 Switching Characteristics Over Recommended Operating Conditions for System Oscillator

		TYP	MAX	UNIT
Start-up time (from power up until oscillating at stable frequency)			2	ms
Oscillation frequency		19.2/24/27/36		MHz
Crystal ESR	19 - 30 MHz		60	Ω
Crystal ESR	30 - 36 MHz		40	Ω
Frequency stability			+/-50	ppm

7.6.2 Clock PLL Electrical Data/Timing (Input and Output Clocks)

Table 7-4 Timing Requirements for MXI1/CLKIN1⁽¹⁾⁽²⁾⁽³⁾ (see Figure 7-6)

NO.			DEVICE			UNIT
NO.			MIN	TYP	MAX	UNIT
1	t_c(MXI1)	Cycle time, MXI1/CLKIN1	27.7		52.083	ns
2	t_w(MXI1H)	Pulse duration, MXI1/CLKIN1 high	0.45C		0.55C	ns
3	t_w(MXI1L)	Pulse duration, MXI1/CLKIN1 low	0.45C		0.55C	ns
4	t_t(MXI1)	Transition time, MXI1/CLKIN1			.05C	ns
5	t_J(MXI1)	Period jitter, MXI1/CLKIN1			.02C	ns

(1) The reference points for the rise and fall transitions are measured at V_IL MAX and V_IH MIN.

(2) C = MXI1/CLKIN1 cycle time in ns. For example, when MXI1/CLKIN1 frequency is 24 MHz use C = 41.6 ns.

(3) tc(MXI1) = 52.083 ns, tc(MXI1) = 41.6 ns, tc(MXI1) = 37.037 ns, and tc(MXI1) = 27.7 ns are the only supported cycle times for MXI1/CLKIN1.

Figure 7-6 MXI1/CLKIN1 Timing

Table 7-5 Switching Characteristics Over Recommended Operating Conditions for CLKOUT0/CLKOUT1⁽¹⁾ ⁽²⁾ (see Figure 7-7)

NO.	PARAMETER		DEVICE			UNIT
NO.	PARAMETER		MIN	TYP	MAX	UNIT
1	t_{C(CLKOUT0/CLKOUT1)}	Cycle time, CLKOUT0/CLKOUT1	27.7			ns
2	t_{w(CLKOUT0H/CLKOUT1H)}	Pulse duration, CLKOUT0/CLKOUT1 high	.45P		.55P	ns
3	t_{w(CLKOUT0L/CLKOUT1L)}	Pulse duration, CLKOUT0/CLKOUT1 low	.45P		.55P	ns
4	t_{t(CLKOUT0/CLKOUT1)}	Transition time, CLKOUT0/CLKOUT1			3	ns
5	t_{d(MXI1H-CLKOUT0H/CLKOUT1H)}	Delay time, MXI1/CLKIN1 high to CLKOUT0/CLKOUT1 high	1		8	ns
6	t_{d(MXI1L-CLKOUT0L/CLKOUT1L)}	Delay time, MXI1/CLKIN1I low to CLKOUT0/CLKOUT1 low	1		8	ns

(1) The reference points for the rise and fall transitions are measured at V_OL MAX and V_OHMIN.

(2) P = 1/CLKOUT0/1 clock frequency in nanoseconds (ns). For example, when CLKOUT1 frequency is 24 MHz use P = 41.6 ns.

Figure 7-7 CLKOUT0/1 Timing

Table 7-6 Switching Characteristics Over Recommended Operating Conditions for CLKOUT2⁽¹⁾ ⁽²⁾ (see Figure 7-8)

NO.	PARAMETER		DEVICE			UNIT
NO.	PARAMETER		MIN	TYP	MAX	UNIT
1	t_C(CLKOUT2)	Cycle time, CLKOUT2	20			ns
2	t_w(CLKOUT2H)	Pulse duration, CLKOUT2 high	.45P		.55P	ns
3	t_w(CLKOUT2L)	Pulse duration, CLKOUT2 low	.45P		.55P	ns
4	t_t(CLKOUT2)	Transition time, CLKOUT2			3	ns
5	t_{d(MXI1H-CLKOUT2H)}	Delay time, MXI1/CLKIN1 high to CLKOUT2 high	1		8	ns
6	t_{d(MXI1L-CLKOUT2L)}	Delay time, MXI1/CLKIN1 low to CLKOUT2 low	1		8	ns

(1) The reference points for the rise and fall transitions are measured at V_OL MAX and V_OH MIN.

(2) P = 1/CLKOUT2 clock frequency in nanoseconds (ns). For example, when CLKOUT2 frequency is 8 MHz use P = 125 ns.

Figure 7-8 CLKOUT2 Timing

7.6.3 PRTCSS Oscillator

The device has an PRTCSS oscillator input/output pair (RTCXI/RTCXO) usable with external crystals or ceramic resonators to provide clock inputs. The optimal frequency for the crystal is 32.768 kHz. The electrical requirements and characteristics are described in this section. Figure 7-9 shows an example circuit.

Figure 7-9 RTCXI1 Oscillator

The load capacitors, C1 and C2, should be chosen such that the equation is satisfied (typical values are C1 = C2 = 10 pF to 20 pF). C_L in the equation below is the load specified by the crystal manufacturer. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator pins (RTCXI and RTCXO) and to the V_{SS_32K} pin.

Equation 1. TMS320DM369 osc_eqsysusb_prs348.gif

7.6.4 PRTCSS Electrical Data/Timing

Table 7-7 Timing Requirements for RTCXI⁽¹⁾ ⁽²⁾ (see Figure 7-6)

NO.			DEVICE			UNIT
NO.			MIN	TYP	MAX
1	t_c(RTCXI)	Cycle time, RTCXI		30.5175		µs
2	t_w(RTCXIH)	Pulse duration, RTCXI high	.45C		.55C	ns
3	t_w(RTCXIL)	Pulse duration, RTCXI low	.45C		.55C	ns

(1) The reference points for the rise and fall transitions are measured at V_IL MAX and V_IH MIN.

(2) C = MXI1/CLKIN1 cycle time in ns. For example, when MXI1/CLKIN1 frequency is 24 MHz use C = 41.6 ns.

Figure 7-10 RTCXI Timing

Table 7-8 Switching Characteristics Over Recommended Operating Conditions for RTC Oscillator

	TYP	MAX	UNIT
Start-up time (from power up until oscillating at stable frequency)	0.85	2	s
Oscillation frequency	32.768		kHz
Crystal ESR		70	kΩ
Frequency stability		+/- 50	ppm

7.7 Power Management and Real Time Clock Subsystem (PRTCSS)

The Power Management and Real Time Clock Subsystem (PRTCSS) is used for calendar applications. The PRTCSS has an independent power supply and can remain ON while the rest of the power supply is turned OFF. The PRTCSS supports the following features:

Real Time Clock (RTC)
- Simple day counter (Up to 89-years)
- To generate the Alarm event to check the RTC count
- 16-bit simple timer
- Watch-dog timer to generate the event for RTC-Sequencer
General Purpose I/O with Anti-chattering
- 3-output pins (PWRCTRO[2:0])
- 7-In/Output pins (PWRCTRIO[6:0])
Interrupt
- 2 RTCSS interrupts (ARMSS and Timer)
- 7 GPIO interrupts (PWRCTRIO[6:0]

7.7.1 PRTCSS Peripheral Register Description

The following table lists the PRTCSS Interface registers (PRTCIF) and Table 7-10 lists the PRTCSS registers which can only be accessed via the PRTCIF registers, their corresponding acronyms, and device memory locations (offsets). For more details, see the TMS320DM36x PRTCSS User's Guide (SPRUFJ0).

Table 7-9 PRTC Interface (PRTCIF) Registers

Offset	Acronym	Register Description
0x0	PID	PRTCIF peripheral ID register
0x4	PRTCIF_CTRL	PRTCIF control register
0x8	PRTCIF_LDATA	PRTCIF access lower data register
0xC	PRTCIF_UDATA	PRTCIF access upper data register
0x10	PRTCIF_INTEN	PRTCIF interrupt enable register
0x14	PRTCIF_INTFLG	PRTCIF interrupt flag register

Table 7-10 Power Management and Real Time Clock Subsystem (PRTCSS) Registers

Offset	Acronym	Register Description
0x0	GO_OUT	Global output pin output data register
0x1	GIO_OUT	Global input/output pin output data register
0x2	GIO_DIR	Global input/output pin direction register
0x3	GIO_IN	Global input/output pin input data register
0x4	GIO_FUNC	Global input/output pin function register
0x5	GIO_RISE_INT_EN	GIO rise interrupt enable register
0x6	GIO_FALL_INT_EN	GIO fall interrupt enable register
0x7	GIO_RISE_INT_FLG	GIO rise interrupt flag register
0x8	GIO_FALL_INT_FLG	GIO fall interrupt flag register
0x9 - 0xA	Reserved	Reserved
0xB	INTC_EXTENA0	EXT interrupt enable 0 register
0xC	INTC_EXTENA1	EXT interrupt enable 1 register
0xD	INTC_FLG0	Event interrupt flag 0 register
0xE	INTC_FLG1	Event interrupt flag 1 register
0x10	RTC_CTRL	RTC control register
0x11	RTC_WDT	Watchdog timer counter register
0x12	RTC_TMR0	Timer counter 0 register
0x13	RTC_TMR1	Timer counter 1 register
0x14	RTC_CCTRL	Calender control register
0x15	RTC_SEC	Seconds register
0x16	RTC_MIN	Minutes register
0x17	RTC_HOUR	Hours register
0x18	RTC_DAY0	Days[[7:0] register
0x19	RTC_DAY1	Days[14:8] register
0x1A	RTC_AMIN	Minutes Alarm register
0x1B	RTC_AHOUR	Hour Alarm register
0x1C	RTC_ADAY0	Days[7:0] Alarm register
0x1D	RTC_ADAY1	Days[14:8] Alarm register
0x20	CLKC_CNT	Clock control register

7.8 General-Purpose Input/Output (GPIO)

The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs. When configured as an output, a write to an internal register can control the state driven on the output pin. When configured as an input, the state of the input is detectable by reading the state of an internal register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices. The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GPIO [0:15]). There are a total of 7 GPIO banks in the device, because the device has 104 GPIOs. For additional details on GPIO pins voltage level and the associated power supply please see Table 7-11.

Table 7-11 GPIO Pin Voltage Level and Power Supply Reference

Voltage Level	1.8 V or 3.3 V			3.3 V	1.8 V
Power Supply Name	V_{DD_AEMIF1_18_33}	V_{DD_AEMIF2_18_33}	V_{DD_ISIF18_33}	V_DDS33	V_{DD18_PRTCSS}
Pin Name	GIO[78:68]	GIO[67]	GIO[103:93]	GIO[92:79]	GIO[110:104]
	GIO[66:56]	GIO[55:52]		GIO[49:0]
	GIO[51:50]

The GPIO peripheral supports the following:

Up to 104 GPIO pins, GPIO[103:0]
Up to 7 GPIO pins dedicated to the PRTC Subsystem. These pins are labeled as PWRCTRIO[6:0]. Only PWRCTRIO[2:0] are connected to the GPIO module, labeled as GPIO[106:104]. For the PRTCSS module the PWRCTRIO[6:0] pins support input and output functionality but for the GPIO module the GPIO[106:104] pins support input functionality only. For more details, see Section 7.7.
Interrupts:
- Up to 15 unique GPIO[15:0] interrupts from Bank 0.
- Up to 3 unique GPIO[106:104] interrupts from Bank 6, dedicated to the PRTC Subsystem. For more details, see Section 7.7.
- Interrupts can be triggered by rising and/or falling edge, specified for each interrupt capable GPIO signal
DMA events:
- Up to 15 unique GPIO DMA events from Bank 0
Set/clear functionality: Firmware writes 1 to corresponding bit position to set or to clear GPIO signal. This lets multiple firmware processes to toggle GPIO output signals without critical section protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to anther process during GPIO programming).
Separate Input/Output registers
Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can be toggled by direct write to the output register.
Output register, when read, reflects output drive status. This, in addition to the input register reflecting pin status, allows wired logic be implemented.

For more detailed information on GPIOs, see the TMS320DM36x Digital Media System-on-Chip (DMSoC) General-Purpose Input/Output (GPIO) User's Guide.

7.8.1 GPIO Peripheral Register Description

Table 7-12 lists the GPIO registers, their corresponding acronyms, and device memory locations (offsets).

Table 7-12 General-Purpose Input/Output (GPIO) Registers

OFFSET	ACRONYM	REGISTER DESCRIPTION
0h	PID	Peripheral Identification Register
8h	BINTEN	GPIO Interrupt Per-Bank Enable Register
GPIO Banks 0 and 1
10h	DIR01	GPIO Banks 0 and 1 Direction Register
14h	OUT_DATA01	GPIO Banks 0 and 1 Output Data Register
18h	SET_DATA01	GPIO Banks 0 and 1 Set Data Register
1Ch	CLR_DATA01	GPIO Banks 0 and 1 Clear Data Register
20h	IN_DATA01	GPIO Banks 0 and 1 Input Data Register
24h	SET_RIS_TRIG	GPIO Set Rising Edge Interrupt Register
28h	CLR_RIS_TRIG	GPIO Clear Rising Edge Interrupt Register
2Ch	SET_FAL_TRIG	GPIO Set Falling Edge Interrupt Register
30h	CLR_FAL_TRIG	GPIO Clear Falling Edge Interrupt Register
34h	INTSTAT	GPIO Interrupt Status Register
GPIO Banks 2 and 3
38h	DIR23	GPIO Banks 2 and 3 Direction Register
3Ch	OUT_DATA23	GPIO Banks 2 and 3 Output Data Register
40h	SET_DATA23	GPIO Banks 2 and 3 Set Data Register
44h	CLR_DATA23	GPIO Banks 2 and 3 Clear Data Register
48h	IN_DATA23	GPIO Banks 2 and 3 Input Data Register
GPIO Bank 4 and 5
60h	DIR45	GPIO Bank 4 and 5 Direction Register
64h	OUT_DATA45	GPIO Bank 4 and 5 Output Data Register
68h	SET_DATA45	GPIO Bank 4 and 5 Set Data Register
6Ch	CLR_DATA45	GPIO Bank 4 and 5 Clear Data Register
70h	IN_DATA45	GPIO Bank 4 and 5 Input Data Register
GPIO Bank 6
88h	DIR6	GPIO Bank 6 Direction Register
8Ch	OUT_DATA6	GPIO Bank 6 Output Data Register
90h	SET_DATA6	GPIO Bank 6 Set Data Register
94h	CLR_DATA6	GPIO Bank 6 Clear Data Register
98h	IN_DATA6	GPIO Bank 6 Input Data Register

7.8.2 GPIO Peripheral Input/Output Electrical Data/Timing

Table 7-13 Timing Requirements for GPIO Inputs (see Figure 7-11)

NO.			DEVICE		UNIT
NO.			MIN	MAX	UNIT
1	t_w(GPIH)	Pulse duration, GPIx high	12P⁽¹⁾		ns
2	t_w(GPIL)	Pulse duration, GPIx low	12P⁽¹⁾		ns

(1) P = PLLC1.SYSCLK4 period, where SYSCLK4 is an output clock of PLLC1. For more details, see Section 4.3, Device Clocking.

Table 7-14 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 7-11)

NO.	PARAMETER		DEVICE		UNIT
NO.	PARAMETER		MIN	MAX	UNIT
3	t_w(GPOH)	Pulse duration, GPOx high	36P⁽¹⁾ - 8		ns
4	t_w(GPOL)	Pulse duration, GPOx low	36P⁽¹⁾ - 8		ns

(1) P = PLLC1.SYSCLK4 period, where SYSCLK4 is an output clock of PLLC1. For more details, see Section 4.3, Device Clocking.

Figure 7-11 GPIO Port Timing

7.8.3 GPIO Peripheral External Interrupts Electrical Data/Timing

Table 7-15 Timing Requirements for External Interrupts/EDMA Events⁽¹⁾ (see Figure 7-12)

NO.			DEVICE		UNIT
NO.			MIN	MAX	UNIT
1	t_w(ILOW)	Width of the external interrupt pulse low	2P⁽²⁾		ns
2	t_w(IHIGH)	Width of the external interrupt pulse high	2P⁽²⁾		ns

(1) The pulse width given is sufficient to generate an interrupt or an EDMA event. However, if a user wants the device to recognize the GPIO changes through software polling of the GPIO register, the GPIO duration must be extended to allow the device enough time to access the GPIO register through the internal bus.

(2) P = PLLC1.SYSCLK4 period, where SYSCLK4 is an output clock of PLLC1. For more details, see Section 4.3, Device Clocking.

Figure 7-12 GPIO External Interrupt Timing

7.9 EDMA Controller

The EDMA controller handles all data transfers between memories and the device slave peripherals on the device. These are summarized as follows:

Transfer to/from on-chip memories
- ARM program/data RAM
- HDVICP Coprocessor memory
- MPEG/JPEG Coprocessor memory
Transfer to/from external storage
- DDR2 / mDDR SDRAM
- Asynchronous EMIF
- OneNAND flash
- NAND flash, NOR flash
- Smart Media, SD, MMC, xD media storage
Transfer to/from peripherals
- McBSP
- SPI
- I2C
- PWM
- RTO
- GPIO
- Timer/WDT
- UART
- MMC/SD

The EDMA Controller consists of two major blocks: the Transfer Controller (TC) and the Channel Controller (CC). The CC is a highly flexible Channel Controller that serves as the user interface and event interface for the EDMA system. The CC supports 64-event channels and 8 QDMA channels. The CC consists of a scalable Parameter RAM (PaRAM) that supports flexible ping-pong, circular buffering, channel-chaining, auto-reloading, and memory protection.

The EDMA Channel Controller has the following features:

Fully orthogonal transfer description
- Three transfer dimensions
- A-synchronized transfers: one dimension serviced per event
- AB- synchronized transfers: two dimensions serviced per event
- Independent indexes on source and destination
- Chaining feature allows 3-D transfer based on single event
Flexible transfer definition
- Increment and constant addressing modes
- Linking mechanism allows automatic PaRAM set update
- Chaining allows multiple transfers to execute with one event
Interrupt generation for:
- DMA completion
- Error conditions
Debug visibility
- Queue watermarking/threshold
- Error and status recording to facilitate debug
64 DMA channels
- Event synchronization
- Manual synchronization (CPU write to event set register)
- Chain synchronization (completion of one transfer chains to next)
8 QDMA channels
- QDMA channels are triggered automatically upon writing to a PaRAM set entry
- Support for programmable QDMA channel to PaRAM mapping
256 PaRAM sets
- Each PaRAM set can be used for a DMA channel, QDMA channel, or link set (remaining)
Four transfer controllers/event queues. The system-level priority of these queues is user programmable
16 event entries per event queue
External events (for example, McBSP TX Evt and RX Evt)

The EDMA Transfer Controller has the following features:

Four transfer controllers
64-bit wide read and write ports per channel
Up to four in-flight transfer requests (TR)
Programmable priority level
Supports two dimensional transfers with independent indexes on source and destination (EDMA Channel Controller manages the Third dimension)
Support for increment and constant addressing modes
Interrupt and error support

Parameter RAM: Each EDMA is specified by an eight word (32-byte) parameter table contained in Parameter RAM (PaRAM) within the CC. The device provides 256 PaRAM entries, one for each of the 64 DMA channels and for 8 QDMA / Linked DMA entries.

DMA Channels: Can be triggered by: " External events (for example, McBSP TX Evt and RX Evt), " Software writing a '1' to the given bit location, or channel, of the Event Set register, or, " Chaining to other DMAs.

QDMA: The Quick DMA (QDMA) function is contained within the CC. The device implements 8 QDMA channels. Each QDMA channel has a selectable PaRAM entry used to specify the transfer. A QDMA transfer is submitted immediately upon writing of the "trigger" parameter (as opposed to the occurrence of an event as with EDMA). The QDMA parameter RAM may be written by any Config bus master through the Config Bus and by DMAs through the Config Bus bridge.

QDMA Channels: Triggered by a configuration bus write to a designated 'QDMA trigger word'. QDMAs allow a minimum number of linear writes (optimized for GEM IDMA feature) to be issued to the CC to force a series of transfers to take place.

7.9.1 EDMA Channel Synchronization Events

The EDMA supports up to 64 EDMA channels which service peripheral devices and external memory. Table 7-16 lists the source of EDMA synchronization events associated with each of the programmable EDMA channels. For the device, the association of an event to a channel is fixed; each of the EDMA channels has one specific event associated with it. These specific events are captured in the EDMA event registers (ER, ERH) even if the events are disabled by the EDMA event enable registers (EER, EERH). For more detailed information on the EDMA module and how EDMA events are enabled, captured, processed, linked, chained, and cleared, etc., see the TMS320DM36x Digital Media System-on-Chip (DMSoC) Enhanced Direct Memory Access (EDMA) Controller User's Guide.

Table 7-16 EDMA Channel Synchronization Events⁽¹⁾ ⁽²⁾

EDMA CHANNEL	EVENT NAME	EVENT DESCRIPTION
0	TIMER3: TEVT6	Timer 3 Interrupt (TEVT6) Event
1	TIMER3 TEVT7	Timer 3 Interrupt (TEVT7) Event
2	McBSP: XEVT or VoiceCodec : VCREVT	McBSP Transmit Event or Voice Codec Transmit Event
3	McBSP :REVT or VoiceCodec : VCREVT	McBSP Receive Event or Voice Codec Receive Event
4	VPSS: EVT1	VPSS Event 1
5	VPSS: EVT2	VPSS Event 2
6	VPSS: EVT3	VPSS Event 3
7	VPSS: EVT4	VPSS Event 4
8	TIMER2: TEVT4	Timer 2 interrupt (TEVT4) Event
9	TIMER2: TEVT5	Timer 2 interrupt (TEVT5) Event
10	SPI2: SPI2XEVT	SPI2 Transmit Event
11	SPI2: SPI2REVT	SPI2 Receive Event
12	MJCP : IMX0INT or HDVICP : HDVICP_ARMINT	MPEG/JPEG Coprocessor IMX0INT Event or High Definition Video Image Coprocessor HDVICP_ARMINT Event
13	MJCP : SEQINT	MPEG/JPEG Coprocessor SEQINT Event
14	SPI1: SPI1XEVT	SPI1 Transmit Event
15	SPI1: SPI1REVT	SPI1 Receive Event
16	SPI0: SPI0XEVT	SP0I Transmit Event
17	SPI0: SPI0REVT	SPI0 Receive Event
18	UART0: URXEVT0 or SPI3: SPI3XEVT	UART 0 Receive Event
19	UART0: UTXEVT0 or SPI3: SPI3REVT	UART 0 Transmit Event
20	UART1: URXEVT1	UART 1 Receive Event
21	UART1: UTXEVT1	UART 1 Transmit Event
22	TIMER4 : TEVT8	Timer 4 (TEVT8) Event
23	TIMER4 : TEVT9	Timer 4 (TEVT9) Event
24	RTOEVT	Real Time Out Module Event
25	GPIO: GPINT9	GPIO 9 Event
26	MMC0RXEVT	MMC/SD0 Receive Event
27	MMC0TXEVT	MMC/SD0 Transmit Event
28	I2C : ICREVT	I2C Receive Event
29	I2C : ICXEVT	I2C Transmit Event
30	MMC1RXEVT	MMC/SD1 Receive Event
31	MMC1TXEVT	MMC/SD1 Transmit Event
32	GPIO :GPINT0	GPIO 0 Event
33	GPIO: GPINT1	GPIO 1 Event
34	GPIO :GPINT2	GPIO 2 Event
35	GPIO :GPINT3	GPIO 3 Event
36	GPIO :GPINT4	GPIO 4 Event
37	GPIO :GPINT5	GPIO 5 Event
38	GPIO :GPINT6	GPIO 6 Event
39	GPIO :GPINT7	GPIO 7 Event
40	GPIO : GPINT10 or EMACRXTHREESH	GPIO 10 Event or EMAC EMACRXTHREESH
41	GPIO : GPINT11 or EMACRXPULSE	GPIO 11 Event or EMAC EMACRXPULSE
42	GPIO : GPINT12 or EMACTXPULSE	GPIO 12 Event or EMAC EMACTXPULSE
43	GPIO : GPINT13 or EMACMISCPULSE	GPIO 13 Event or EMAC EMACMISCPULSE
44	GPIO : GPINT14	GPIO 14 Event
45	GPIO : GPINT15	GPIO 15 Event
46	ADC : ADINT	Analog to Digital Converter Interrupt Event
47	GPIO : GPINT8	GPIO 8 Event
48	TIMER0 : TEVT0	Timer 0 (TEVT0) Event
49	TIMER0: TEVT1	Timer 1 (TEVT1) Event
50	TIMER1: TEVT2	Timer 2(TEVT2) Event
51	TIMER1: TEVT3	Timer 3(TEVT3) Event
52	PWM0	PWM 0 Event
53	PWM1 or MJCP : IMX1INT	PWM 1 Event or MJCP IMX1INT interrupt
54	PWM2 or MJCP : NSFINT	PWM 2 Event or MJCP NSFINT interrupt
55	PWM3 or HDVICP(6) : CP_UNDEF	MPEG/JPEG Coprocessor PWM 3 Event or High Definition Video Image Coprocessor CP_UNDEF Event
56	MJCP : VLCDINT or HDVICP(5) : CP_ECDCMP	MPEG/JPEG Coprocessor VLCDINT Event or High Definition Video Image Coprocessor CP_ECDCMP Event
57	MJCP : BIMINT or HDVICP(8) : CP_ME	MPEG/JPEG Coprocessor BIMINT Event or High Definition Video Image Coprocessor CP_ME Event
58	MJCP : DCTINT or HDVICP(1) : CP_CALC	MPEG/JPEG Coprocessor DCTINT Event or High Definition Video Image Coprocessor CP_CALC Event
59	MJCP : QIQINT or HDVICP(7) : CP_IPE	MPEG/JPEG Coprocessor QIQINT Event or High Definition Video Image Coprocessor CP_IPE Event
60	MJCP : BPSINT or HDVICP(2) : CP_BS	MPEG/JPEG Coprocessor BPSINT Event or High Definition Video Image Coprocessor CP_BS Event
61	MJCP : VLCDERRINT or HDVICP(0) : CP_LPF	MPEG/JPEG Coprocessor VLCDERRINT Event or High Definition Video Image Coprocessor CP_LPF Event
62	MJCP : RCNTINT or HDVICP(3) : CP_MC	MPEG/JPEG Coprocessor RCNTINT Event or High Definition Video Image Coprocessor CP_MC Event
63	MJCP : COPCINT or HDVICP(4) : CP_ECDEND	MPEG/JPEG Coprocessor COPCINT Event or High Definition Video Image Coprocessor CP_ECDEND Event

(1) In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or intermediate transfer completion events. For more detailed information on EDMA event-transfer chaining, see the Document Support section for the Enhanced Direct Memory Access (EDMA) Controller User's Guide.

(2) The total number of EDMA events exceeds 64, which is the maximum value of the EDMA module. Therefore, several events are multiplexed and you must use the register EDMA_EVTMUX in the System Control Module to select the event source for multiplexed events. See the TMS320DM36x DMSoC ARM Subsystem User's Guide (SPRUFG5) for more information on the System Control Module register EDMA_EVTMUX.

7.9.2 EDMA Peripheral Register Description

Table 7-17 lists the EDMA registers, their corresponding acronyms, and device memory locations (offsets).

Table 7-17 EDMA Registers

Offset	Acronym	Register Description
00h	PID	Peripheral Identification Register
04h	CCCFG	EDMA3CC Configuration Register
Global Registers
0200h	QCHMAP0	QDMA Channel 0 Mapping Register
0204h	QCHMAP1	QDMA Channel 1 Mapping Register
0208h	QCHMAP2	QDMA Channel 2 Mapping Register
020Ch	QCHMAP3	QDMA Channel 3 Mapping Register
0210h	QCHMAP4	QDMA Channel 4 Mapping Register
0214h	QCHMAP5	QDMA Channel 5 Mapping Register
0218h	QCHMAP6	QDMA Channel 6 Mapping Register
021Ch	QCHMAP7	QDMA Channel 7 Mapping Register
0240h	DMAQNUM0	DMA Queue Number Register 0
0244h	DMAQNUM1	DMA Queue Number Register 1
0248h	DMAQNUM2	DMA Queue Number Register 2
024Ch	DMAQNUM3	DMA Queue Number Register 3
0250h	DMAQNUM4	DMA Queue Number Register 4
0254h	DMAQNUM5	DMA Queue Number Register 5
0258h	DMAQNUM6	DMA Queue Number Register 6
025Ch	DMAQNUM7	DMA Queue Number Register 7
0260h	QDMAQNUM	QDMA Queue Number Register
0284h	QUEPRI	Queue Priority Register
0300h	EMR	Event Missed Register
0304h	EMRH	Event Missed Register High
0308h	EMCR	Event Missed Clear Register
030Ch	EMCRH	Event Missed Clear Register High
0310h	QEMR	QDMA Event Missed Register
0314h	QEMCR	QDMA Event Missed Clear Register
0318h	CCERR	EDMA3CC Error Register
031Ch	CCERRCLR	EDMA3CC Error Clear Register
0320h	EEVAL	Error Evaluate Register
0340h	DRAE0	DMA Region Access Enable Register for Region 0
0344h	DRAEH0	DMA Region Access Enable Register High for Region 0
...
0350h	DRAE2	DMA Region Access Enable Register for Region 2
0354h	DRAEH2	DMA Region Access Enable Register High for Region 2
0360h	DRAE4	DMA Region Access Enable Register for Region 4
0364h	DRAEH4	DMA Region Access Enable Register High for Region 4
0368h	DRAE5	DMA Region Access Enable Register for Region 5
036Ch	DRAEH5	DMA Region Access Enable Register High for Region 5
0380h	QRAE0	QDMA Region Access Enable Register for Region 0
0388h	QRAE2	QDMA Region Access Enable Register for Region 2
0390h	QRAE4
0394h	QRAE5
0400h-047Ch	Q0E0-Q1E15	Event Queue Entry Registers Q0E0-Q1E15
0600h	QSTAT0	Queue 0 Status Register
0604h	QSTAT1	Queue 1 Status Register
0608h	QSTAT2	Queue 2 Status Register
060Ch	QSTAT3	Queue 3 Status Register
0620h	QWMTHRA	Queue Watermark Threshold A Register
0640h	CCSTAT	EDMA3CC Status Register
Global Channel Registers
1000h	ER	Event Register
1004h	ERH	Event Register High
1008h	ECR	Event Clear Register
100Ch	ECRH	Event Clear Register High
1010h	ESR	Event Set Register
1014h	ESRH	Event Set Register High
1018h	CER	Chained Event Register
101Ch	CERH	Chained Event Register High
1020h	EER	Event Enable Register
1024h	EERH	Event Enable Register High
1028h	EECR	Event Enable Clear Register
102Ch	EECRH	Event Enable Clear Register High
1030h	EESR	Event Enable Set Register
1034h	EESRH	Event Enable Set Register High
1038h	SER	Secondary Event Register
103Ch	SERH	Secondary Event Register High
1040h	SECR	Secondary Event Clear Register
1044h	SECRH	Secondary Event Clear Register High
1050h	IER	Interrupt Enable Register
1054h	IERH	Interrupt Enable Register High
1058h	IECR	Interrupt Enable Clear Register
105Ch	IECRH	Interrupt Enable Clear Register High
1060h	IESR	Interrupt Enable Set Register
1064h	IESRH	Interrupt Enable Set Register High
1068h	IPR	Interrupt Pending Register
106Ch	IPRH	Interrupt Pending Register High
1070h	ICR	Interrupt Clear Register
1074h	ICRH	Interrupt Clear Register High
1078h	IEVAL	Interrupt Evaluate Register
1080h	QER	QDMA Event Register
1084h	QEER	QDMA Event Enable Register
1088h	QEECR	QDMA Event Enable Clear Register
108Ch	QEESR	QDMA Event Enable Set Register
1090h	QSER	QDMA Secondary Event Register
1094h	QSECR	QDMA Secondary Event Clear Register
Shadow Region 0 Channel Registers
2000h	ER	Event Register
2004h	ERH	Event Register High
2008h	ECR	Event Clear Register
200Ch	ECRH	Event Clear Register High
2010h	ESR	Event Set Register
2014h	ESRH	Event Set Register High
2018h	CER	Chained Event Register
201Ch	CERH	Chained Event Register High
2020h	EER	Event Enable Register
2024h	EERH	Event Enable Register High
2028h	EECR	Event Enable Clear Register
202Ch	EECRH	Event Enable Clear Register High
2030h	EESR	Event Enable Set Register
2034h	EESRH	Event Enable Set Register High
2038h	SER	Secondary Event Register
203Ch	SERH	Secondary Event Register High
2040h	SECR	Secondary Event Clear Register
2044h	SECRH	Secondary Event Clear Register High
2050h	IER	Interrupt Enable Register
2054h	IERH	Interrupt Enable Register High
2058h	IECR	Interrupt Enable Clear Register
205Ch	IECRH	Interrupt Enable Clear Register High
2060h	IESR	Interrupt Enable Set Register
2064h	IESRH	Interrupt Enable Set Register High
2068h	IPR	Interrupt Pending Register
206Ch	IPRH	Interrupt Pending Register High
2070h	ICR	Interrupt Clear Register
2074h	ICRH	Interrupt Clear Register High
2078h	IEVAL	Interrupt Evaluate Register
2080h	QER	QDMA Event Register
2084h	QEER	QDMA Event Enable Register
2088h	QEECR	QDMA Event Enable Clear Register
208Ch	QEESR	QDMA Event Enable Set Register
2090h	QSER	QDMA Secondary Event Register
2094h	QSECR	QDMA Secondary Event Clear Register
Shadow Region 1 Channel Registers
2200h	ER	Event Register
2204h	ERH	Event Register High
2208h	ECR	Event Clear Register
220Ch	ECRH	Event Clear Register High
2210h	ESR	Event Set Register
2214h	ESRH	Event Set Register High
2218h	CER	Chained Event Register
221Ch	CERH	Chained Event Register High
2220h	EER	Event Enable Register
2224h	EERH	Event Enable Register High
2228h	EECR	Event Enable Clear Register
222Ch	EECRH	Event Enable Clear Register High
2230h	EESR	Event Enable Set Register
2234h	EESRH	Event Enable Set Register High
2238h	SER	Secondary Event Register
223Ch	SERH	Secondary Event Register High
2240h	SECR	Secondary Event Clear Register
2244h	SECRH	Secondary Event Clear Register High
2250h	IER	Interrupt Enable Register
2254h	IERH	Interrupt Enable Register High
2258h	IECR	Interrupt Enable Clear Register
225Ch	IECRH	Interrupt Enable Clear Register High
2260h	IESR	Interrupt Enable Set Register
2264h	IESRH	Interrupt Enable Set Register High
2268h	IPR	Interrupt Pending Register
226Ch	IPRH	Interrupt Pending Register High
2270h	ICR	Interrupt Clear Register
2274h	ICRH	Interrupt Clear Register High
2278h	IEVAL	Interrupt Evaluate Register
2280h	QER	QDMA Event Register
2284h	QEER	QDMA Event Enable Register
2288h	QEECR	QDMA Event Enable Clear Register
228Ch	QEESR	QDMA Event Enable Set Register
2290h	QSER	QDMA Secondary Event Register
2294h	QSECR	QDMA Secondary Event Clear Register
2400h-2494h	—	Shadow Region 2 Channel Registers
2600h-2694h	—	Shadow Region 3 Channel Registers
2800h-2894h		Shadow Region 4 Channel Registers
2A00h-2A94h		Shadow Region 5 Channel Registers
2C00h-2C94h		Shadow Region 6 Channel Registers
2E00h-2E94h		Shadow Region 7 Channel Registers
4000h-4FFFh	—	Parameter RAM (PaRAM)

Table 7-18 shows an abbreviation of the set of registers which make up the parameter set for each of 512 EDMA events. Each of the parameter register sets consist of 8 32-bit word entries. Table 7-19 shows the parameter set entry registers with relative memory address locations within each of the parameter sets.

Table 7-18 EDMA Parameter Set RAM

HEX ADDRESS RANGE	DESCRIPTION
0x01C0 4000 - 0x01C0 401F	Parameters Set 0 (8 32-bit words)
0x01C0 4020 - 0x01C0 403F	Parameters Set 1 (8 32-bit words)
0x01C0 4040 - 0x01C0 405F	Parameters Set 2 (8 32-bit words)
0x01C0 4060 - 0x01C0 407F	Parameters Set 3 (8 32-bit words)
0x01C0 4080 - 0x01C0 409F	Parameters Set 4 (8 32-bit words)
0x01C0 40A0 - 0x01C0 40BF	Parameters Set 5 (8 32-bit words)
...	...
0x01C0 7FC0 - 0x01C0 7FDF	Parameters Set 510 (8 32-bit words)
0x01C0 7FE0 - 0x01C0 7FFF	Parameters Set 511 (8 32-bit words)

Table 7-19 Parameter Set Entries

HEX OFFSET ADDRESS WITHIN THE PARAMETER SET	ACRONYM	PARAMETER ENTRY
0x0000	OPT	Option
0x0004	SRC	Source Address
0x0008	A_B_CNT	A Count, B Count
0x000C	DST	Destination Address
0x0010	SRC_DST_BIDX	Source B Index, Destination B Index
0x0014	LINK_BCNTRLD	Link Address, B Count Reload
0x0018	SRC_DST_CIDX	Source C Index, Destination C Index
0x001C	CCNT	C Count

7.10 External Memory Interface (EMIF)

The device supports several memory and external device interfaces, including:

Asynchronous EMIF (AEMIF) for interfacing to SRAM.
- OneNAND flash memories
- NAND flash memories
- NOR flash memories
DDR2/mDDR Memory Controller for interfacing to SDRAM.

7.10.1 Asynchronous EMIF (AEMIF)

The EMIF supports the following features:

SRAM, NOR flash, etc. on up to 2 asynchronous chip selects addressable up to 16MB each
Supports 8-bit or 16-bit data bus widths
Programmable asynchronous cycle timings
Supports extended wait mode
Supports Select Strobe mode

7.10.1.1 NAND (NAND, SmartMedia, xD)

The NAND features of the EMIF are as follows:

NAND flash on up to 2 asynchronous chip selects
8 and 16-bit data bus widths
Programmable cycle timings
Performs 1-bit and 4-bit ECC calculation
NAND Mode also supports SmartMedia/SSFDC (Solid State Floppy Disk Controller) and xD memory cards

7.10.1.2 OneNAND

The OneNAND features supported are as follows.

NAND flash on up to 2 asynchronous chip selects
Only 16-bit data bus widths
Supports asynchronous writes and reads
Supports synchronous reads with continuous linear burst mode (Does not support synchronous reads with wrap burst modes)
Programmable cycle timings for each chip select in asynchronous mode

7.10.1.3 EMIF Peripheral Register Descriptions

Table 7-20 lists the EDMA registers, their corresponding acronyms, and device memory locations (offsets).

Table 7-20 External Memory Interface (EMIF) Registers

OFFSET	ACRONYM	REGISTER DESCRIPTION
04h	AWCCR	Asynchronous Wait Cycle Configuration Register
10h	A1CR	Asynchronous 1 Configuration Register (CE0 space)
14h	A2CR	Asynchronous 2 Configuration Register (CE1 space)
40h	EIRR	EMIF Interrupt Raw Register
44h	EIMR	EMIF Interrupt Mask Register
48h	EIMSR	EMIF Interrupt Mask Set Register
4Ch	EIMCR	EMIF Interrupt Mask Clear Register
5Ch	ONENANDCTL	OneNAND Flash Control Register
60h	NANDFCR	NAND Flash Control Register
64h	NANDFSR	NAND Flash Status Register
70h	NANDF1ECC	NAND Flash 1-Bit ECC Register 1 (CE0 Space)
74h	NANDF2ECC	NAND Flash 1-Bit ECC Register 2 (CE1 Space)
BCh	NAND4BITECCLOAD	NANDFlash 4-Bit ECC Load Register
C0h	NAND4BITECC1	NAND Flash 4-Bit ECC Register 1
C4h	NAND4BITECC2	NAND Flash 4-Bit ECC Register 2
C8h	NAND4BITECC3	NAND Flash 4-Bit ECC Register 3
CCh	NAND3BITECC4	NAND Flash 4-Bit ECC Register 4
D0h	NANDERRADD1	NAND Flash 4-Bit ECC Error Address Register 1
D4h	NANDERRADD2	NAND Flash 4-Bit ECC Error Address Register 2
D8h	NANDERRVAL1	NAND Flash 4-Bit ECC Error Value Register 1
DCh	NANDERRVAL2	NAND Flash 4-Bit ECC Error Value Register 2

7.10.1.4 AEMIF Electrical Data/Timing

Table 7-21 Timing Requirements for Asynchronous Memory Cycles for AEMIF Module⁽¹⁾ (see Figure 7-13 and Figure 7-14)

NO.			DEVICE			UNIT
NO.			MIN	NOM	MAX	UNIT
READS and WRITES
2	t_{w(EM_WAIT)}	Pulse duration, EM_WAIT assertion and deassertion	2E			ns
READS
12	t_{su(EMDV-EMOEH)}	Setup time, EM_D[15:0] valid before EM_OE high	4			ns
13	t_{h(EMOEH-EMDIV)}	Hold time, EM_D[15:0] valid after EM_OE high	3			ns
14	t_su _{(EMOEL-EMWAIT)}	Setup time EM_WAIT asserted before EM_OE high⁽²⁾		4E + 3		ns
READS (OneNAND Synchronous Burst Read)
30	t_{su(EMDV-EMCLKH)}	Setup time, EM_D[15:0] valid before EM_CLK high	4			ns
31	t_{h(EMCLKH-EMDIV)}	Hold time, EM_D[15:0] valid after EM_CLK high	3			ns
WRITES
28	t_su _{(EMWEL-EMWAIT)}	Setup time EM_WAIT asserted before EM_WE high⁽²⁾		4E + 3		ns

(1) E=2*PLL1C SYSCLK4 period in ns. See Section 4.3 for more information.

(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended wait states. Figure 7-15 and Figure 7-16 describe EMIF transactions that include extended wait states inserted during the STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles.

Table 7-22 Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for AEMIF Module⁽¹⁾ ⁽²⁾ ⁽³⁾ (see Figure 7-13 and Figure 7-14)

NO.	PARAMETER		DEVICE			UNIT
NO.	PARAMETER		MIN	TYP	MAX	UNIT
READS and WRITES
1	t_{d(TURNAROUND)}	Turn around time		(TA)*E		ns
READS
3	t_c(EMRCYCLE)	EMIF read cycle time (EW = 0)		(RS+RST+RH + 3)*E		ns
3	t_c(EMRCYCLE)	EMIF read cycle time (EW = 1)		(RS+RST+RH+3)*E		ns
4	t_{su(EMCEL-EMOEL)}	Output setup time, EM_CE[1:0] low to EM_OE low (SS = 0)		(RS + 1)*E + 3		ns
4	t_{su(EMCEL-EMOEL)}	Output setup time, EM_CE[1:0] low to EM_OE low (SS = 1)		(RS + 1)*E		ns
5	t_{h(EMOEH-EMCEH)}	Output hold time, EM_OE high to EM_CE[1:0] high (SS = 0)		(RH + 1)*E		ns
5	t_{h(EMOEH-EMCEH)}	Output hold time, EM_OE high to EM_CE[1:0] high (SS = 1)		(RH + 1)*E		ns
6	t_{su(EMBAV-EMOEL)}	Output setup time, EM_BA[1:0] valid to EM_OE low		(RS + 1)*E		ns
7	t_{h(EMOEH-EMBAIV)}	Output hold time, EM_OE high to EM_BA[1:0] invalid		(RH + 1)*E		ns
8	t_{su(EMBAV-EMOEL)}	Output setup time, EM_A[21:0] valid to EM_OE low		(RS + 1)*E		ns
9	t_{h(EMOEH-EMAIV)}	Output hold time, EM_OE high to EM_A[21:0] invalid		(RH + 1)*E		ns
10	t_w(EMOEL)	EM_OE active low width (EW = 0)		(RST)*E		ns
10	t_w(EMOEL)	EM_OE active low width (EW = 1)		(RST+(EWC16))E		ns
11	t_{d(EMWAITH-EMOEH)}	Delay time from EM_WAIT deasserted to EM_OE high		4E		ns
READS (OneNAND Synchronous Burst Read)
32	f_{c(EM_CLK)}	Frequency, EM_CLK			66	MHz
33	t_{c(EM_CLK)}	Cycle time, EM_CLK	15.15			ns
34	t_{su(EM_ADVV-EM_CLKH)}	Output setup time, EM_ADV valid before EM_CLK high	2E - 2.5			ns
35	t_{h(EM_CLKH-EM_ADVIV)}	Output hold time, EM_CLK high to EM_ADV invalid	2E + 3			ns
36	t_{su(EM_AV-EM_CLKH)}	Output setup time, EM_A[21:0]/EM_BA[1] valid before EM_CLK high	2E - 2.5			ns
37	t_{h(EM_CLKH-EM_AIV)}	Output hold time, EM_CLK high to EM_A[21:0]/EM_BA[1] invalid	2E + 3			ns
38	t_{w(EM_CLKH)}	Pulse duration, EM_CLK high	5.05			ns
39	t_{w(EM_CLKL)}	Pulse duration, EM_CLK low	5.05			ns
WRITES
15	t_c(EMWCYCLE)	EMIF write cycle time (EW = 0)	(WS + WST + WH + TA + 4) * E - 3		(WS + WST + WH + TA + 4) * E + 3	ns
15	t_c(EMWCYCLE)	EMIF write cycle time (EW = 1)	(WS + WST + WH + TA + 4) * E - 3		(WS + WST + WH + TA + 4) * E + 3	ns
16	t_{su(EMCEL-EMWEL)}	Output setup time, EM_CE[1:0] low to EM_WE low (SS = 0)	(WS+1) * E - 3			ns
16	t_{su(EMCEL-EMWEL)}	Output setup time, EM_CE[1:0] low to EM_WE low (SS = 1)	(WS+1) * E - 3			ns
17	t_{h(EMWEH-EMCEH)}	Output hold time, EM_WE high to EM_CE[1:0] high (SS = 0)	(WH+1) * E - 3			ns
17	t_{h(EMWEH-EMCEH)}	Output hold time, EM_WE high to EM_CE[1:0] high (SS = 1)	(WH+1) * E - 3			ns
20	t_{su(EMBAV-EMWEL)}	Output setup time, EM_BA[1:0] valid to EM_WE low	(WS+1) * E - 3			ns
21	t_{h(EMWEH-EMBAIV)}	Output hold time, EM_WE high to EM_BA[1:0] invalid	(WH+1) * E - 3			ns
22	t_{su(EMAV-EMWEL)}	Output setup time, EM_A[21:0] valid to EM_WE low	(WS+1) * E - 3			ns
23	t_{h(EMWEH-EMAIV)}	Output hold time, EM_WE high to EM_A[21:0] invalid	(WH+1) * E - 3			ns
24	t_w(EMWEL)	EM_WE active low width (EW = 0)	(WST+1) * E - 3			ns
24	t_w(EMWEL)	EM_WE active low width (EW = 1)	(WST+1) * E - 3			ns
25	t_{d(EMWAITH-EMWEH)}	Delay time from EM_WAIT deasserted to EM_WE high			4E + 3	ns
26	t_{su(EMDV-EMWEL)}	Output setup time, EM_D[15:0] valid to EM_WE low	(WS+1) * E - 3			ns
27	t_{h(EMWEH-EMDIV)}	Output hold time, EM_WE high to EM_D[15:0] invalid	(WH+1) * E - 3			ns

(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-1], RH[8-1], WS[16-1], WST[64-1], WH[8-1], and MEW[1-256]. See the TMS320DM36x Digital Media System-on-Chip (DMSoC) Asynchronous External Memory Interface (EMIF) User's Guide (SPRUFI1) for more information.

(2) E=2*PLL1C SYSCLK4 period in ns. See Section 4.3 for more information.

(3) EWC = external wait cycles determined by EM_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See the TMS320DM36x Digital Media System-on-Chip (DMSoC) Asynchronous External Memory Interface (EMIF) User's Guide (SPRUFI1) for more information.

Figure 7-13 Asynchronous Memory Read Timing for EMIF

Figure 7-14 Asynchronous Memory Write Timing for EMIF

Figure 7-15 EM_WAIT Read Timing Requirements

Figure 7-16 EM_WAIT Write Timing Requirements

Figure 7-17 Synchronous OneNAND Flash Read Timing

7.10.2 DDR2/mDDR Memory Controller

The DDR2/mDDR Memory Controller is a dedicated interface to DDR2 / mDDR SDRAM. It supports JESD79D-2A standard compliant DDR2 SDRAM devices and compliant Mobile DDR SDRAM devices. DDR2 / mDDR SDRAM plays a key role in a device-based system. Such a system is expected to require a significant amount of high-speed external memory for all of the following functions:

Buffering of input image data from sensors or video sources
Intermediate buffering for processing/resizing of image data in the VPFE
Numerous OSD display buffers
Intermediate buffering for large raw Bayer data image files while performing image processing functions
Buffering for intermediate data while performing video encode and decode functions
Storage of executable code for the ARM

The DDR2/mDDR Memory Controller supports the following features:

JESD79D-2A standard compliant DDR2 SDRAM
Mobile DDR SDRAM
256 MByte memory space
Data bus width 16 bits
CAS latencies:
- DDR2: 2, 3, 4, and 5
- mDDR: 2 and 3
Internal banks:
- DDR2: 1, 2, 4, and 8
- mDDR: 1, 2, and 4
Burst length: 8

Burst type: sequential

1 CS signal
Page sizes: 256, 512, 1024, and 2048
SDRAM autoinitialization
Self-refresh mode
Partial array self-refresh (for mDDR)
Power down mode
Prioritized refresh
Programmable refresh rate and backlog counter
Programmable timing parameters
Little endian

For details on the DDR2/mDDR Memory Controller, see the TMS320DM36x Digital Media System-on-Chip (DMSoC) DDR2/mDDR Memory Controller User's Guide (SPRUFI2).

7.10.3 DDR2/mDDR Memory Controller Electrical Data/Timing

Table 7-23 Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory Controller⁽¹⁾ ⁽²⁾(see Figure 7-18)

NO.	PARAMETER			MIN	MAX	UNIT
1	t_{f(DDR_CLK)}	Frequency, DDR_CLK	340-DDR2 (supported for 432-MHz device)	90	340	MHz
			mDDR (supported for 432-MHz device)	90	168

(1) DDR_CLK = PLLC1.SYSCLK7/2 or PLLC2.SYSCLK3/2.

(2) The PLL2 Controller must be programmed such that the resulting DDR_CLK clock frequency is within the specified range.

Figure 7-18 DDR2 Memory Controller Clock Timing

7.10.3.1 DDR2/mDDR Routing Specifications

7.10.3.1.1 DDR2/mDDR Interface

This section provides the timing specification for the DDR2/mDDR interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR2/mDDR memory system without the need for a complex timing closure process. For more information regarding guidelines for using this DDR2 specification, see the Understanding TI's PCB Routing Rule-Based DDR2 Timing Specification (SPRAAV0).

7.10.3.1.2 DDR2/mDDR Interface Schematic

Figure 7-19 shows the DDR2/mDDR interface schematic for a single-memory DDR2/mDDR system. The dual-memory system shown in Figure 7-20. Pin numbers for the device can be obtained from the pin description section.

A. Vio 1.8 is the power supply for the DDR2/mDDR memories and the DM36x DDR2/mDDR interface.

B. One of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin. In the Case of mobile DDR, these capacitors can be eliminated completely.

C. When present, A13 signals should be connected.

D. VREF applies in the case of DDR2 memories. For mDDR the DMSoC DDR_VREF pin still needs to be connected to the divider circuit.

Figure 7-19 DDR2/mDDR Single-Memory High Level Schematic

A. Vio 1.8 is the power supply for the DDR2/mDDR memories and the DM36x DDR2/mDDR interface.

B. One of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin. In the Case of mobile DDR, these capacitors can be eliminated completely.

C. When present, A13 signals should be connected.

D. VREF applies in the case of DDR2 memories. For mDDR the DMSoC DDR_VREF pin still needs to be connected to the divider circuit.

Figure 7-20 DDR2/mDDR Dual-Memory High Level Schematic

7.10.3.1.3 Compatible JEDEC DDR2/mDDR Devices

Table 7-24 shows the parameters of the JEDEC DDR2/mDDR devices that are compatible with this interface. Generally, the DDR2/mDDR interface is compatible with x16 DDR2/mDDR devices.

The device also supports JEDEC DDR2/mDDR x8 devices in the dual chip configuration. In this case, one chip supplies the upper byte and the second chip supplies the lower byte. Addresses and most control signals are shared just like regular dual chip memory configurations.

Table 7-24 Compatible JEDEC DDR2/mDDR Devices

No.	Parameter	Min	Max	Unit	Notes
1	JEDEC DDR2/mDDR Device Speed Grade	DDR2-800 (for 340MHz DDR2)			See Notes ⁽¹⁾, ⁽³⁾
		mDDR-400 (for 168MHz mDDR)			See Notes ⁽¹⁾, ⁽⁴⁾
2	JEDEC DDR2/mDDR Device Bit Width	x8	x16	Bits
3	JEDEC DDR2/mDDR Device Count	1	2	Devices	See Note ⁽²⁾

(1) Higher DDR2/mDDR speed grades are supported due to inherent JEDEC DDR2/mDDR backwards compatibility.

(2) Supported configurations are one 16-bit DDR2/mDDR memory or two 8-bit DDR2/mDDR memories.

(3) Used for DDR2.

(4) Used for mobile DDR.

7.10.3.1.4 PCB Stack Up

The minimum stack up required for routing the device is a six layer stack as shown in Table 7-25. Additional layers may be added to the PCB stack up to accommodate other circuitry or to reduce the size of the PCB footprint.

Table 7-25 Minimum PCB Stack Up

Layer	Type	Description
1	Signal	Top Routing Mostly Horizontal
2	Plane	Ground
3	Plane	Power
4	Signal	Internal Routing
5	Plane	Ground
6	Signal	Bottom Routing Mostly Vertical

Complete stack up specifications are provided below.

Table 7-26 PCB Stack Up Specifications⁽³⁾

No.	Parameter	Min	Typ	Max	Unit	Notes
1	PCB Routing/Plane Layers		6
2	Signal Routing Layers		3
3	Full ground layers under DDR2/mDDR routing region	2
4	Number of ground plane cuts allowed within DDR routing region			0
5	Number of ground reference planes required for each DDR2/mDDR routing layer	1
6	Number of layers between DDR2/mDDR routing layer and reference ground plane			0
7	PCB Routing Feature Size		4		Mils
8	PCB Trace Width w		4		Mils
9	PCB BGA escape via pad size		18		Mils
10	PCB BGA escape via hole size		8		Mils
11	DMSoC Device BGA pad size					See Note ⁽⁴⁾
12	DDR2/mDDR Device BGA pad size					See Note ⁽¹⁾
13	Single Ended Impedance, Zo	50		75	Ω
14	Impedance Control	Z-5	Z	Z+5	Ω	See Note ⁽²⁾

(1) Please see the DDR2/mDDR device manufacturer documentation for the DDR2/mDDR device BGA pad size.

(2) Z is the nominal singled ended impedance selected for the PCB specified by item 13.

(3) Consult the PCB fabricator to determine their preference for escape via size.

(4) Please refer to the Flip Chip Ball Grid Array Package Reference Guide (SPRU811) for DMSoC device BGA pad size.

7.10.3.1.5 Placement

Figure 7-21 shows the required placement for the device and the DDR2/mDDR devices. The dimensions for Figure 7-21 are defined in Table 7-27. The placement does not restrict the side of the PCB that the devices are mounted on. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. For single-memory DDR2/mDDR systems, the second DDR2/mDDR device is omitted from the placement.

Figure 7-21 DM369 and DDR2/mDDR Device Placement

Table 7-27 Placement Specifications

No.	Parameter	Min	Max	Unit	Notes
1	X		1750	Mils	See Notes ⁽¹⁾, ⁽²⁾
2	Y		1280	Mils	See Notes ⁽¹⁾, ⁽²⁾
3	Y Offset		650	Mils	See Notes ⁽¹⁾. ⁽²⁾, ⁽³⁾
4	DDR2/mDDR Keepout Region				See Note ⁽⁴⁾
5	Clearance from non-DDR2/mDDR signal to DDR2/mDDR Keepout Region	4		w	See Note ⁽⁵⁾

(1) See Figure 7-19 for dimension definitions.

(2) Measurements from center of DMSoC device to center of DDR2/mDDR device.

(3) For single memory systems it is recommended that Y Offset be as small as possible.

(4) DDR2/mDDR Keepout region to encompass entire DDR2/mDDR routing area

(5) Non-DDR2/mDDR signals allowed within DDR2/mDDR keepout region provided they are separated from DDR2/mDDR routing layers by a ground plane.

7.10.3.1.6 DDR2/mDDR Keep Out Region

The region of the PCB used for the DDR2/mDDR circuitry must be isolated from other signals. The DDR2/mDDR keep out region is defined for this purpose and is shown in Figure 7-22. The size of this region varies with the placement and DDR routing. Additional clearances required for the keep out region are shown in Table 7-27.

Figure 7-22 DDR2/mDDR Keepout Region

7.10.3.1.7 Bulk Bypass Capacitors

Bulk bypass capacitors are required for moderate speed bypassing of the DDR2/mDDR and other circuitry. Table 7-28 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this table only covers the bypass needs of the DMSoC and DDR2/mDDR interfaces. Additional bulk bypass capacitance may be needed for other circuitry.

Table 7-28 Bulk Bypass Capacitors

No.	Parameter	Min	Unit	Notes
1	V_{DD18_DDR} Bulk Bypass Capacitor Count	3	Devices	See Note ⁽¹⁾
2	V_{DD18_DDR} Bulk Bypass Total Capacitance	30	uF
3	DDR#1 Bulk Bypass Capacitor Count	1	Devices	See Note ⁽¹⁾
4	DDR#1 Bulk Bypass Total Capacitance	22	uF
5	DDR#2 Bulk Bypass Capacitor Count	1	Devices	See Notes ⁽¹⁾, ⁽²⁾
6	DDR#2 Bulk Bypass Total Capacitance	22	uF	See Note ⁽²⁾

(1) These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed (HS) bypass caps.

(2) Only used on dual-memory systems

7.10.3.1.8 High-Speed Bypass Capacitors

High-speed (HS) bypass capacitors are critical for proper DDR2/mDDR interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass cap, DMSoC/DDR2/mDDR power, and DMSoC/DDR2/mDDR ground connections. Table 7-29 contains the specification for the HS bypass capacitors and for the power connections on the PCB.

Table 7-29 High-Speed Bypass Capacitors

No.	Parameter	Min	Max	Unit	Notes
1	HS Bypass Capacitor Package Size		0402	10 Mils	See Note ⁽¹⁾
2	Distance from HS bypass capacitor to device being bypassed		250	Mils
3	Number of connection vias for each HS bypass capacitor	2		Vias	See Note ⁽⁴⁾
4	Trace length from bypass capacitor contact to connection via	1	30	Mils
5	Number of connection vias for each DDR2/mDDR device power or ground balls	1		Vias
6	Trace length from DDR2/mDDR device power ball to connection via		35	Mils
7	V_{DD18_DDR} HS Bypass Capacitor Count	10		Devices	See Note ⁽²⁾
8	V_{DD18_DDR} HS Bypass Capacitor Total Capacitance	1.2		uF
9	DDR#1 HS Bypass Capacitor Count	8		Devices	See Note ⁽²⁾
10	DDR#1 HS Bypass Capacitor Total Capacitance	0.4		uF
11	DDR#2 HS Bypass Capacitor Count	8		Devices	See Notes ⁽²⁾, ⁽³⁾
12	DDR#2 HS Bypass Capacitor Total Capacitance	0.4		uF	See Note ⁽³⁾

(1) LxW, 10 mil units, i.e., a 0402 is a 40x20 mil surface mount capacitor

(2) These devices should be placed as close as possible to the device being bypassed.

(3) Only used on dual-memory systems

(4) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.

7.10.3.1.9 Net Classes

Table 7-30 lists the clock net classes for the DDR2/mDDR interface. Table 7-31 lists the signal net classes, and associated clock net classes, for the signals in the DDR2/mDDR interface. These net classes are used for the termination and routing rules that follow.

Table 7-30 Clock Net Class Definitions

Clock Net Class	DMSoC Pin Names
CK	DDR_CLK/DDR_CLK
DQS0	DDR_DQS0/DDR_DQSN0
DQS1	DDR_DQS1/DDR_DQSN1

Table 7-31 Signal Net Class Definitions

Clock Net Class	Associated Clock Net Class	DMSoC Pin Names
ADDR_CTRL	CK	DDR_BA[2:0], DDR_A[13:0], DDR_CS, DDR_CAS, DDR_RAS, DDR_WE, DDR_CKE
DQ0	DQS0	DDR_DQ[7:0], DDR_DQM0
DQ1	DQS1	DDR_DQ[15:8], DDR_DQM1
DQGATE	CK, DQS0, DQS1	DDR_DQGATE0, DDR_DQGATE1

7.10.3.1.10 DDR2/mDDR Signal Termination

No terminations of any kind are required in order to meet signal integrity and overshoot requirements. Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only type permitted. Table 7-32 shows the specifications for the series terminators.

Table 7-32 DDR2/mDDR Signal Terminations

No.	Parameter	Typ	Max	Unit	Notes
1	CK Net Class		10	Ω	See Note ⁽¹⁾
2	ADDR_CTRL Net Class	22	Zo	Ω	See Notes ⁽¹⁾, ⁽²⁾, ⁽³⁾
3	Data Byte Net Classes (DQS0-DQS1, DQ0-DQ1)	22	Zo	Ω	See Notes ⁽¹⁾, ⁽²⁾, ⁽³⁾, ⁽⁴⁾
4	DQGATE Net Class (DQGATE)	10	Zo	Ω	See Notes ⁽¹⁾, ⁽²⁾, ⁽³⁾

(1) Only series termination is permitted, parallel or SST specifically disallowed.

(2) Terminator values larger than typical only recommended to address EMI issues.

(3) Termination value should be uniform across net class.

(4) When no termination is used on data lines (0 Ωs), the DDR2/mDDR devices must be programmed to operate in 60% strength mode.

7.10.3.1.11 VREF Routing

VREF is used as a reference by the input buffers of the DDR2/mDDR memories and the device. VREF is intended to be the DDR2/mDDR power supply voltage and should be created using a resistive divider as shown in Figure 7-19. Other methods of creating VREF are not recommended. Figure 7-23 shows the layout guidelines for VREF.

Figure 7-23 VREF Routing and Topology

7.10.3.1.12 DDR2/mDDR CK and ADDR_CTRL Routing

Figure 7-24 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A should be maximized.

Figure 7-24 CK and ADDR_CTRL Routing and Topology

Table 7-33 CK and ADDR_CTRL Routing Specification ⁽¹⁾

No	Parameter	Min	Typ	Max	Unit	Notes
1	Center to center DQS-DQSN spacing			2w
2	CK A to B/A to C Skew Length Mismatch			25	Mils	See Note ⁽¹⁾
3	CK B to C Skew Length Mismatch			25	Mils
4	Center to center CK to other DDR2/mDDR trace spacing	4w				See Note ⁽³⁾
5	CK/ADDR_CTRL nominal trace length	CACLM-50	CACLM	CACLM+50	Mils	See Note ⁽²⁾
6	ADDR_CTRL to CK Skew Length Mismatch			100	Mils
7	ADDR_CTRL to ADDR_CTRL Skew Length Mismatch			100	Mils
8	Center to center ADDR_CTRL to other DDR2/mDDR trace spacing	4w				See Note ⁽³⁾
9	Center to center ADDR_CTRL to other ADDR_CTRL trace spacing	3w				See Note ⁽³⁾
10	ADDR_CTRL A to B/A to C Skew Length Mismatch			100	Mils	See Note ⁽¹⁾
11	ADDR_CTRL B to C Skew Length Mismatch			100	Mils

(1) Series terminator, if used, should be located closest to DMSoC.

(2) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.

(3) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion.

Figure 7-25 shows the topology and routing for the DQS and DQ net classes; the routes are point to point. Skew matching across bytes is not needed nor recommended.

Figure 7-25 DQS and DQ Routing and Topology

Table 7-34 DQS and DQ Routing Specification

No.	Parameter	Min	Typ	Max	Unit	Notes
1	Center to center DQS-DQSN spacing			2w
2	DQS E Skew Length Mismatch			25	Mils
3	Center to center DQS to other DDR2/mDDR trace spacing	4w				See Note ⁽⁴⁾
4	DQS/DQ nominal trace length	DQLM-50	DQLM	DQLM+50	Mils	See Notes ⁽¹⁾, ⁽³⁾
5	DQ to DQS Skew Length Mismatch			100	Mils	See Note ⁽³⁾
6	DQ to DQ Skew Length Mismatch			100	Mils	See Note ⁽³⁾
7	DQ to DQ/DQS via Count Mismatch			1	Vias	⁽²⁾⁽³⁾
8	Center to center DQ to other DDR2/mDDR trace spacing	4w				See Notes ⁽⁴⁾,⁽⁵⁾
9	Center to Center DQ to other DQ trace spacing	3w				See Notes ⁽²⁾, ⁽⁴⁾
10	DQ/DQS E Skew Length Mismatch			100	Mils	See Note ⁽³⁾

(1) Series terminator, if used, should be located closest to DDR.

(2) DQLM is the longest Manhattan distance of each of the DQS and DQ net classes.

(3) There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and data byte 1.

(4) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion.

(5) DQ's from other DQS domains are considered other DDR2/mDDR trace.

Figure 7-26 shows the routing for the DQGATE net classes. Table 7-35 contains the routing specification.

Figure 7-26 DQGATE Routing

Table 7-35 DQGATE Routing Specification

No.	Parameter	Min	Typ	Max	Unit	Notes
1	DQGATE Length F		CKB0B1			See Note ⁽¹⁾
3	Center to center DQGATE to any other trace spacing	4w
4	DQS/DQ nominal trace length	DQLM-50	DQLM	DQLM+50	Mils
5	DQGATE Skew			100	Mils	See Note ⁽²⁾

(1) CKB0B1 is the sum of the length of the CK net plus the average length of the DQS0 and DQS1 nets.

(2) Skew from CKB0B1

7.11 MMC/SD

The device includes MMC/SD Controllers which are compliant with MMC V3.31, Secure Digital Part 1 Physical Layer Specification V1.1 and Secure Digital Input Output (SDIO) V2.0 specifications.

The device MMC/SD Controller has following features:

MultiMediaCard (MMC)
Secure Digital (SD) Memory Card
MMC/SD protocol support
SDIO protocol support
Programmable clock frequency
512 bit Read/Write FIFO to lower system overhead
Slave EDMA transfer capability
SD High Capacity support

The device MMC/SD Controller does not support SPI mode.

7.11.1 MMC/SD Peripheral Register Description

Table 7-36 lists the MMC/SD registers, their corresponding acronyms, and device memory locations (offsets).

Table 7-36 Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers

OFFSET	ACRONYM	REGISTER DESCRIPTION
00h	MMCCTL	MMC Control Register
04h	MMCCLK	MMC Memory Clock Control Register
08h	MMCST0	MMC Status Register 0
0Ch	MMCST1	MMC Status Register 1
10h	MMCIM	MMC Interrupt Mask Register
14h	MMCTOR	MMC Response Time-Out Register
18h	MMCTOD	MMC Data Read Time-Out Register
1Ch	MMCBLEN	MMC Block Length Register
20h	MMCNBLK	MMC Number of Blocks Register
24h	MMCNBLC	MMC Number of Blocks Counter Register
28h	MMCDRR	MMC Data Receive Register
2Ch	MMCDXR	MMC Data Transmit Register
30h	MMCCMD	MMC Command Register
34h	MMCARGHL	MMC Argument Register
38h	MMCRSP01	MMC Response Register 0 and 1
3Ch	MMCRSP23	MMC Response Register 2 and 3
40h	MMCRSP45	MMC Response Register 4 and 5
44h	MMCRSP67	MMC Response Register 6 and 7
48h	MMCDRSP	MMC Data Response Register
50h	MMCCIDX	MMC Command Index Register
64h	SDIOCTL	SDIO Control Register
68h	SDIOST0	SDIO Status Register 0
6Ch	SDIOIEN	SDIO Interrupt Enable Register
70h	SDIOIST	SDIO Interrupt Status Register
74h	MMCFIFOCTL	MMC FIFO Control Register

7.11.2 MMC/SD Electrical Data/Timing

Table 7-37 Timing Requirements for MMC/SD Module
(see Figure 7-28 and Figure 7-30)

NO.			DEVICE				UNIT
			FAST MODE		STANDARD MODE
			MIN	MAX	MIN	MAX
1	t_{su(CMDV-CLKH)}	Setup time, SD_CMD valid before SD_CLK high	2.7		2.7		ns
2	t_h(CLKH-CMDV)	Hold time, SD_CMD valid after SD_CLK high	2.5		2.5		ns
3	t_{su(DATV-CLKH)}	Setup time, SD_DATx valid before SD_CLK high	2.7		2.7		ns
4	t_h(CLKH-DATV)	Hold time, SD_DATx valid after SD_CLK high	2.5		2.5		ns

Table 7-38 Switching Characteristics Over Recommended Operating Conditions for MMC/SD Module (see Figure 7-27 through Figure 7-30)

NO.	PARAMETER		DEVICE				UNIT
			FAST MODE		STANDARD MODE
			MIN	MAX	MIN	MAX
7	f_(CLK)	Operating frequency, SD_CLK	0	50	0	25	MHz
8	f_{(CLK_ID)}	Identification mode frequency, SD_CLK	0	400	0	400	KHz
9	t_W(CLKL)	Pulse width, SD_CLK low	6.5		6.5		ns
10	t_W(CLKH)	Pulse width, SD_CLK high	6.5		6.5		ns
11	t_r(CLK)	Rise time, SD_CLK		3		3	ns
12	t_f(CLK)	Fall time, SD_CLK		3		3	ns
13	t_d(CLKL-CMD)	Delay time, SD_CLK low to SD_CMD transition	-4.1	1.5	-4.1	1.5	ns
14	t_d(CLKL-DAT)	Delay time, SD_CLK low to SD_DATx transition	-4.1	1.5	-4.1	1.5	ns

Figure 7-27 MMC/SD Host Command Timing

Figure 7-28 MMC/SD Card Response Timing

Figure 7-29 MMC/SD Host Write Timing

Figure 7-30 MMC/SD Host Read and Card CRC Status Timing

7.12 Video Processing Subsystem (VPSS) Overview

The device contains a Video Processing Subsystem (VPSS) that provides an input interface (Video Processing Front End or VPFE) for external imaging peripherals such as image sensors, video decoders, etc.; and an output interface (Video Processing Back End or VPBE) for display devices, such as analog SDTV/HDTV displays, digital LCD panels, etc.

In addition to these peripherals, there is a set of common buffer memory and DMA control to ensure efficient use of the DDR2/mDDR burst bandwidth. The shared buffer logic/memory is a unique block that is tailored for seamlessly integrating the VPSS into an image/video processing system. It acts as the primary source or sink to all the VPFE and VPBE modules that are either requesting or transferring data from/to DDR2/mDDR . In order to efficiently use the external DDR2/mDDR bandwidth, the shared buffer logic/memory interfaces with the DMA system via a high bandwidth bus (64-bit wide). The shared buffer logic/memory also interfaces with all the VPFE and VPBE modules via a 128-bit wide bus. The shared buffer logic/memory (divided into the read & write buffers and arbitration logic) is capable of performing the following functions. It is imperative that the VPSS use DDR2/mDDR bandwidth efficiently due to both its large bandwidth requirements and the real-time requirements of the VPSS modules. Because it is possible to configure the VPSS modules in such a way that DDR2/mDDR bandwidth is exceeded, a set of user accessible registers is provided to monitor overflows or failures in data transfers.

7.12.1 Video Processing Front-End (VPFE)

The VPFE or Video Processing Front-End block is comprised of the Image Sensor Interface (ISIF), Image Pipe (IPIPE), Image Pipe Interface (IPIPEIF), Hardware 3A Statistic Generator (H3A), and a Hardware Face Detect Engine. These modules are described in the sections that follow.

The VPFE sub-module register memory mapping is shown in Table 7-39.

Table 7-39 Video Processing Front End Sub-Module Register Map

Address:Offset	Acronym	Register Description
0x01C7:0000	ISP	ISP System Configuration
0x01C7:0200	VPBE_CLK_CTRL	VPBE Clock Control
0x01C7:0400	RSZ	Resizer
0x01C7:0800	IPIPE	Image Pipe
0x01C7:1000	ISIF	Image Sensor Interface
0x01C7:1200	IPIPEIF	Image Pipe Interface
0x01C7:1400	H3A	Hardware 3A
0x01C7:1600 - 0x01C7:17FF	Reserved	Reserved
0x01C7:1800	FDIF	Face Detection Register Interface
0x01C7:1C00	OSD	VPBE On-Screen Display
0x01C7:1D00 - 0x01C7:1DFF	Reserved	Reserved
0x01C7:1E00	VENC	VPBE Video Encoder
0x01C7:2000 - 0x01CF:FFFF	Reserved	Reserved

7.12.1.1 Image Sensor Interface (ISIF)

The ISIF is responsible for accepting raw (unprocessed) image/video data from a sensor (CMOS or CCD). In addition, the ISIF can accept YUV video data in numerous formats, typically from so-called video decoder devices. In case of raw inputs, the ISIF output requires additional image processing to transform the raw input image to the final processed image. This processing can be done either on-the-fly in IPIPE or in software on the ARM and MPEG/JPEG and HD Video Image coprocessor subsystems. In parallel, raw data input to the ISIF can also used for computing various statistics (H3A, Histogram) to eventually control the image/video tuning parameters. The ISIF is programmed via control and parameter registers. The following features are supported by the ISIF module.

Support for conventional Bayer pattern, pixel summation mode, and RGB stripe sensor formats.
Support for the various pixel summation mode formats is provided via a data reformatter of ISIF, which transforms any specific sensor formats to the Bayer format. The maximum line width supported by the reformatter is 4736 pixels.
Image processing steps applicable to RGB stripe sensors are limited to color-dependent gain control and black level offset control."
Generates HD/VD timing signals and field ID to an external timing generator, or can synchronize to the external timing generator.
Support for progressive and interlaced sensors (hardware support for up to 2 fields and firmware support for higher number of fields, typically 3-, 4-, and 5-field sensors.
Support for up to 32K pixels (image size) in both the horizontal and vertical direction.
Support for up to 120 MHz sensor clock.
Support for ITU-R BT.656/1120 standard format.
Support for YCbCr 422 format, either 8- or 16-bit with discrete HSYNC and VSYNC signals.
Support for up to 16-bit input.
Support for color space conversion.
Digital clamp with Horizontal/Vertical offset drift compensation.
Vertical Line defect correction based on a lookup table that contains defect position.
Support for color-dependent gain control and black level offset control.
Ability to control output to the DDR2/mDDR via an external write enable signal.
Support for down sampling via programmable culling patterns.
Support for 12-bit to 8-bit DPCM compression.
Support for 10-bit to 8-bit A-law compression.
Support for generating output to range 16-bits, 12-bits, and 8-bits wide (8-bits wide allows for 50% saving in storage area).
OTF DPC
Noise Filter
2D edge enhancement

The ISIF register memory mapping (offsets) is shown in Table 7-40.

Table 7-40 Image Sensor Interface (ISIF) Registers

Offset	Acronym	Register Description
0h	SYNCEN	Synchronization Enable
4h	MODESET	Mode Setup
8h	HDW	HD pulse width
Ch	VDW	VD pulse width
10h	PPLN	Pixels per line
14h	LPFR	Lines per frame
18h	SPH	Start pixel horizontal
1Ch	LNH	Number of pixels in line
20h	SLV0	Start line vertical - field 0
24h	SLV1	Start line vertical - field 1
28h	LNV	Number of lines vertical
2Ch	CULH	Culling - horizontal
30h	CULV	Culling - vertical
34h	HSIZE	Horizontal size
38h	SDOFST	SDRAM Line Offset
3Ch	CADU	SDRAM Address - high
40h	CADL	SDRAM Address - low
44h - 48h	Reserved	Reserved
4Ch	CCOLP	CCD Color Pattern
50h	CRGAIN	CCD Gain Adjustment - R/Ye
54h	CGRGAIN	CCD Gain Adjustment - Gr/Cy
58h	CGBGAIN	CCD Gain Adjustment - Gb/G
5Ch	CBGAIN	CCD Gain Adjustment - B/Mg
60h	COFSTA	CCD Offset Adjustment
64h	FLSHCFG0	FLSHCFG0
68h	FLSHCFG1	FLSHCFG1
6Ch	FLSHCFG2	FLSHCFG2
70h	VDINT0	VD Interrupt #0
74h	VDINT1	VD Interrupt #1
78h	VDINT2	VD Interrupt #2
7Ch	Reserved	Reserved
80h	CGAMMAWD	Gamma Correction settings
84h	REC656IF	CCIR 656 Control
88h	CCDCFG	CCD Configuration
8Ch	DFCCTL	Defect Correction - Control
90h	VDFSATLV	Defect Correction - Vertical Saturation Level
94h	DFCMEMCTL	Defect Correction - Memory Control
98h	DFCMEM0	Defect Correction - Set V Position
9Ch	DFCMEM1	Defect Correction - Set H Position
A0h	DFCMEM2	Defect Correction - Set SUB1
A4h	DFCMEM3	Defect Correction - Set SUB2
A8h	DFCMEM4	Defect Correction - Set SUB3
ACh	CLAMPCFG	Black Clamp configuration
B0h	CLDCOFST	DC offset for Black Clamp
B4h	CLSV	Black Clamp Start position
B8h	CLHWIN0	Horizontal Black Clamp configuration
BCh	CLHWIN1	Horizontal Black Clamp configuration
C0h	CLHWIN2	Horizontal Black Clamp configuration
C4h	CLVRV	Vertical Black Clamp configuration
C8h	CLVWIN0	Vertical Black Clamp configuration
CCh	CLVWIN1	Vertical Black Clamp configuration
D0h	CLVWIN2	Vertical Black Clamp configuration
D4h	CLVWIN3	Vertical Black Clamp configuration
D8h - 1A2h	Reserved	Reserved
1A4h	CSCCTL	Color Space Converter Enable
1A8h	CSCM0	Color Space Converter - Coefficients #0
1ACh	CSCM1	Color Space Converter - Coefficients #1
1B0h	CSCM2	Color Space Converter - Coefficients #2
1B4h	CSCM3	Color Space Converter - Coefficients #3
1B8h	CSCM4	Color Space Converter - Coefficients #4
1BCh	CSCM5	Color Space Converter - Coefficients #5
1C0h	CSCM6	Color Space Converter - Coefficients #6
1C4h	CSCM7	Color Space Converter - Coefficients #7

7.12.1.2 The Image Pipe Interface (IPIPEIF)

The IPIPEIF is data and sync signals interface module for ISIF and IPIPE. Data source of this module is sensor parallel port, ISIF or SDRAM and the selected data is output to ISIF and IPIPE. This module also outputs black frame subtraction (two-way) data which is generated by subtracting SDRAM data from sensor parallel port or ISIF data and vice versa. Depending on the functions performed, it may also readjust the HD, VD, and PCLK timing to the IPIPE and/or ISIF input.

The IPIPEIF module supports the following features:

Up to 16-bit sensor data input
Dark-frame subtract of raw image stored in SDRAM from image coming from sensor parallel port or ISIF
8-10, 8-12 DPCM decompression of 10-8, 12-8 compressed data in SDRAM
Inverse ALAW decompression of RAW data from SDRAM
(1,2,1) average filtering before horizontal decimation
Horizontal decimation (downsizing) of input lines to <= 2160 maximum required by the IPIPE
Gain multiply for output data to IPIPE
Simple defect correction to prevent a subtraction of defect pixel
8-bit, 12-bit unpacking of 8-bit, 12-bit packed SDRAM data

The IPIPE register memory mapping (offsets) is shown in Table 7-41.

Table 7-41 Image Pipe Input Interface (IPIPEIF) Registers

Address	Acronym	Register Description
0h	ENABLE	IPIPE I/F Enable
4h	CFG1	IPIPE I/F Configuration
8h	PPLN	IPIPE I/F Interval of HD / Start pixel in HD
Ch	LPFR	IPIPE I/F Interval of VD / Start line in VD
10h	HNUM	IPIPE I/F Number of valid pixels per line
14h	VNUM	IPIPE I/F Number of valid lines per frame
18h	ADDRU	IPIPE I/F Memory Address (Upper)
1Ch	ADDRL	IPIPE I/F Memory Address (Lower)
20h	ADOFS	IPIPE I/F Address offset of each line
24h	RSZ	IPIPE I/F Horizontal Resizing Parameter
28h	GAIN	IPIPE I/F Gain Parameter
2Ch	DPCM	IPIPE I/F DPCM Configuration
30h	CFG2	IPIPE I/F Configuration 2
34h	INIRSZ	IPIPE I/F Initial position of resize
38h	OCLIP	IPIPE I/F Output clipping value
3Ch	DTUDF	IPIPE I/F Data underflow error status
40h	CLKDIV	IPIPE I/F Clock rate configuration
44h	DPC1	IPIPE I/F Defect pixel correction
48h	DPC2	IPIPE I/F Defect pixel correction
54h	RSZ3A	IPIPE I/F Horizontal Resizing Parameter for H3A
58h	INIRSZ3A	IPIPE I/F Initial position of resize for H3A

7.12.1.3 Image Pipe – Hardware Image Signal Processor (IPIPE)

The Image Pipe (IPIPE) is a programmable hardware image processing module that generates image data in YCbCr-4:2:2 or YCbCr-4:2:0 formats from raw CCD/CMOS data. An image resizer is also fully integrated within this module. The IPIPE can also be configured to operate in a resize-only mode, which allows YCbCr-4:2:2 or YCbCr-4:2:0 to be resized without processing every module in the IPIPE.

The following features are supported by the IPIPE:

12-bit RAW data image processing or 16-bit YCbCr resizing
RGB Bayer pattern for input color filter array; does not support complementary color pattern, stripe pattern, or Foveon™ sensors.
Requires at least eight pixels for horizontal blanking and four lines for vertical blanking. In one shot mode, 16 blanking lines after processing area are required.
Maximum horizontal and vertical offset of IPIPE processing area from synchronous signal is 65534
Maximum input and output widths up to 2176 pixels wide (1088 for RSZ[2]).
Raw pass-through mode for images wider than 2176 pixels (up to 8190 pixels)
Automatic mirroring of pixels/lines when edge processing is performed so that the width and height is consistent throughout.
Defect pixel correction using
- Lookup table method that contains row and column position of the pixel to be corrected
- On-the-fly adaptive method
Offset and gain control for white balancing at each color component (WB).
CFA interpolation for good quality CFA interpolation
Programmable RGB to RGB blending matrix (9 coefficients for the 3x3 matrix). (RGB2RGB module)
Separate lookup tables for gamma correction on each of R, G and B components for display through piece-wise linear interpolation approach
4:4:4 data to 4:2:2 data conversion by chroma low-pass filtering and down sampling to Cb and Cr. (4:4:4 to 4:2:2 module)
Programmable look-up table for luminance edge enhancement. Adjustable brightness and contrast for Y component (Edge Enhancer module)
Programmable down or up-sampling filter for both horizontal and vertical directions with range from 1/16x to 16x, in which the filter outputs two images with different magnification simultaneously (Resizer module)
4:2:2 to 4:2:0 conversion that can be done in the resizing block
Different data formats [YCbCr (4:2:2 or 4:2:0), RGB (32bit/16bit), Raw data] are available while storing data in the SDRAM from IPIPE
Flipping image horizontally and/or vertically
Programmable histogram engine (4 windows, 256 bins)
Boxcar calculation (1/8 or 1/16 size).

The IPIPE register memory mapping (offsets) is shown in Table 7-42.

Table 7-42 IPIPE Registers

Offset	Acronym	Register Description
0h	SRC_EN	IPIPE Enable
04h	SRC_MODE	One Shot Mode
08h	SRC_FMT	Input/Output Data Paths
Ch	SRC_COL	Color Pattern
10h	SRC_VPS	Vertical Start Position
14h	SRC_VSZ	Vertical Processing Size
18h	SRC_HPS	Horizontal Start Position
1Ch	SRC_HSZ	Horizontal Processing Size
24h	DMA_STA	Status Flags (Reserved)
48h	GCK_MMR	MMR Gated Clock Control
2Ch	GCK_PIX	PCLK Gated Clock Control
30h	Reserved	Reserved
34h	DPC_LUT_EN	LUTDPC (=LUT Defect Pixel Correction): Enable
38h	DPC_LUT_SEL	LUTDPC: Processing Mode Selection
3Ch	DPC_LUT_ADR	LUTDPC: Start Address in LUT
40h	DPC_LUT_SIZ	LUTDPC: Number of available entries in LUT
1D0h	WB2_OFT_R	WB2 (=White Balance): Offset
1D4h	WB2_OFT_GR	WB2: Offset
1D8h	WB2_OFT_GB	WB2: Offset
1DCh	WB2_OFT_B	WB2: Offset
1E0h	WB2_WGN_R	WB2: Gain
1E4h	WB2_WGN_GR	WB2: Gain
1E8h	WB2_WGN_GB	WB2: Gain
1ECh	WB2_WGN_B	WB2: Gain
1F0h-228h	Reserved	Reserved
22Ch	RGB1_MUL_RR	RGB1 (=1st RGB2RGB conv): Matrix Coefficient
230h	RGB1_MUL_GR	RGB1: Matrix Coefficient
234h	RGB1_MUL_BR	RGB1: Matrix Coefficient
238h	RGB1_MUL_RG	RGB1: Matrix Coefficient
23Ch	RGB1_MUL_GG	RGB1: Matrix Coefficient
240h	RGB1_MUL_BG	RGB1: Matrix Coefficient
244h	RGB1_MUL_RB	RGB1: Matrix Coefficient
248h	RGB1_MUL_GB	RGB1: Matrix Coefficient
24Ch	RGB1_MUL_BB	RGB1: Matrix Coefficient
250h	RGB1_OFT_OR	RGB1: Offset
254h	RGB1_OFT_OG	RGB1: Offset
258h	RGB1_OFT_OB	RGB1: Offset
25Ch	GMM_CFG	Gamma Correction Configuration
294h	YUV_ADJ	YUV (RGB2YCbCr conv): Luminance Adjustment (contrast & brightness)
298h	YUV_MUL_RY	YUV: Matrix Coefficient
29Ch	YUV_MUL_GY	YUV: Matrix Coefficient
2A0h	YUV_MUL_BY	YUV: Matrix Coefficient
2A4h	YUV_MUL_RCB	YUV: Matrix Coefficient
2A8h	YUV_MUL_GCB	YUV: Matrix Coefficient
2ACh	YUV_MUL_BCB	YUV: Matrix Coefficient
2B0h	YUV_MUL_RCR	YUV: Matrix Coefficient
2B4h	YUV_MUL_GCR	YUV: Matrix Coefficient
2B8h	YUV_MUL_BCR	YUV: Matrix Coefficient
2BCh	YUV_OFT_Y	YUV: Offset
2C0h	YUV_OFT_CB	YUV: Offset
2C4h	YUV_OFT_CR	YUV: Offset
2C8h	YUV_PHS	Chrominance Position (for 422 down sampler)
2D4h	YEE_EN	YEE (=Edge Enhancer): Enable
2D8h	YEE_TYP	YEE: Method Selection
2DCh	YEE_SHF	YEE: HPF Shift Length
2E0h	YEE_MUL_00	YEE: HPF Coefficient
2E4h	YEE_MUL_01	YEE: HPF Coefficient
2E8h	YEE_MUL_02	YEE: HPF Coefficient
2ECh	YEE_MUL_10	YEE: HPF Coefficient
2F0h	YEE_MUL_11	YEE: HPF Coefficient
2F4h	YEE_MUL_12	YEE: HPF Coefficient
2F8h	YEE_MUL_20	YEE: HPF Coefficient
2FCh	YEE_MUL_21	YEE: HPF Coefficient
300h	YEE_MUL_22	YEE: HPF Coefficient
304h	YEE_THR	YEE: Lower Threshold before referring to LUT
308h	YEE_E_GAN	YEE: Edge Sharpener Gain
30Ch	YEE_E_THR_1	YEE: Edge Sharpener HP Value Lower Threshold
310h	YEE_E_THR_2	YEE: Edge Sharpener HP Value Upper Limit
314h	YEE_G_GAN	YEE: Edge Sharpener Gain on Gradient
318h	YEE_G_OFT	YEE: Edge Sharpener Offset on Gradient
380h	BOX_EN	BOX (=Boxcar) Enable
384h	BOX_MODE	BOX: One Shot Mode
388h	BOX_TYP	BOX: Block Size (16x16 or 8x8)
38Ch	BOX_SHF	BOX: Down shift value of input
390h	BOX_SDR_SAD_H	BOX: SDRAM Address MSB
394h	BOX_SDR_SAD_L	BOX: SDRAM Address LSB
398h	Reserved	Reserved
39Ch	HST_EN	HST (=Histogram): Enable
3A0h	HST_MODE	HST: One Shot Mode
3A4h	HST_SEL	HST: Source Select
3A8h	HST_PARA	HST: Parameters Select
3ACh	HST_0_VPS	HST: Vertical Start Position
3B0h	HST_0_VSZ	HST: Vertical Size
3B4h	HST_0_HPS	HST: Horizontal Start Position
3B8h	HST_0_HSZ	HST: Horizontal Size
3BCh	HST_1_VPS	HST: Vertical Start Position
3C0h	HST_1_VSZ	HST: Vertical Size
3C4h	HST_1_HPS	HST: Horizontal Start Position
3C8h	HST_1_HSZ	HST: Horizontal Size
3CCh	HST_2_VPS	HST: Vertical Start Position
3D0h	HST_2_VSZ	HST: Vertical Size
3D4h	HST_2_HPS	HST: Horizontal Start Position
3D8h	HST_2_HSZ	HST: Horizontal Size
3DCh	HST_3_VPS	HST: Vertical Start Position
3E0h	HST_3_VSZ	HST: Vertical Size
3E4h	HST_3_HPS	HST: Horizontal Start Position
3E8h	HST_3_HSZ	HST: Horizontal Size
3ECh	HST_TBL	HST: Table Select
3F0h	HST_MUL_R	HST: Matrix Coefficient
3F4h	HST_MUL_GR	HST: Matrix Coefficient
3F8h	HST_MUL_GB	HST: Matrix Coefficient
3FCh	HST_MUL_B	HST: Matrix Coefficient

7.12.1.4 Hardware 3A (H3A)

The H3A module is designed to support the control loops for Auto Focus, Auto White Balance and Auto Exposure by collecting metrics about the imaging/video data. The metrics are to adjust the various parameters for processing the imaging/video data. There are 2 main blocks in the H3A module:

Auto Focus (AF) engine
Auto Exposure (AE) Auto White Balance (AWB) engine

The AF engine extracts and filters the red, green, and blue data from the input image/video data and provides either the accumulation or peaks of the data in a specified region. The specified region is a two-dimensional block of data and is referred to as a "paxel" for the case of AF.

The AE/AWB Engine accumulates the values and checks for saturated values in a sub sampling of the video data. In the case of the AE/AWB, the two-dimensional block of data is referred to as a "window". Thus, other than referring them by different names, a paxel and a window are essentially the same thing. However, the number, dimensions, and starting position of the AF paxels and the AE/AWB windows are separately programmable.

The following features are supported by the AF engine:

Support for input from DDR2 / mDDR SDRAM (in addition to the ISIF port)
Support for a Peak Mode in a Paxel (a Paxel is defined as a two dimensional block of pixels).
Accumulate the maximum Focus Value of each line in a Paxel
Support for an Accumulation/Sum Mode (instead of Peak mode).
Accumulate Focus Value in a Paxel.
Support for up to 36 Paxels in the horizontal direction and up to 128 Paxels in the vertical direction. The number of horizontal paxels is limited by the memory size (and cost), while the vertical number of paxels is not. Therefore, the number of paxels in horizontal direction is smaller than the number of paxels in vertical direction.
Programmable width and height for the Paxel. All paxels in the frame will be of same size.
Programmable red, green, and blue position within a 2x2 matrix.
Separate horizontal start for paxel and filtering.
Programmable vertical line increments within a paxel.
Parallel IIR filters configured in a dual-biquad configuration with individual coefficients (2 filters with 11 coefficients each). The filters are intended to compute the sharpness/peaks in the frame to focus on.

The following features are supported by the AE/AWB engine:

Support for input from DDR2 / mDDR SDRAM (in addition to the ISIF port)
Accumulate clipped pixels along with all non-saturated pixels
Support for up to 36 horizontal windows.
Support for up to 128 vertical windows.
Programmable width and height for the windows. All windows in the frame will be of same size.
Separate vertical start co-ordinate and height for a black row of paxels that is different than the remaining color paxels.
Programmable Horizontal Sampling Points in a window
Programmable Vertical Sampling Points in a window

The Hardware 3A (H3A) register memory mapping (offsets) is shown in Table 7-43.

Table 7-43 Hardware 3A Statistics Generation (AE, AF, AWB) (H3A) Registers

Offset	Acronym	Register Description
0h	PID	Peripheral Revision and Class Information
4h	PCR	Peripheral Control Register
8h	AFPAX1	Setup for the AF Engine Paxel Configuration
Ch	AFPAX2	Setup for the AF Engine Paxel Configuration
10h	AFPAXSTART	Start Position for AF Engine Paxels
18h	AFBUFST	SDRAM/DDRAM Start address for AF Engine
4Ch	AEWWIN1	Configuration for AE/AWB Windows
50h	AEWINSTART	Start position for AE/AWB Windows
54h	AEWINBLK	Start position and height for black line of AE/AWB Windows
58h	AEWSUBWIN	Configuration for subsample data in AE/AWB window
5Ch	AEWBUFST	SDRAM/DDRAM Start address for AE/AWB Engine Output Data
60h	RSDR_ADDR	AE/AWB Engine Configuration
64h	LINE_START	Line start position for ISIF interface
68h	VFV_CFG1	AF Vertical Focus Configuration 1 Register
6Ch	VFV_CFG2	AF Vertical Focus Configuration 2 Register
70h	VFV_CFG3	AF Vertical Focus Configuration 3 Register
74h	VFV_CFG4	AF Vertical Focus Configuration 4 Register
78h	HFV_THR	Configures the Horizontal Thresholds for the AF IIR filters

7.12.1.5 Face Detection Module

The following features are supported on the Face Detection module:

High detection rate of close to 100% under most conditions
Allows detection in different directions - up, left, and right
Allows detection with rotation in plane (RIP) - ±45°, @ 0°/+90°/-90°
Allows detection for rotation out of plane (ROP)
- Horizontal (left/right) pan: ±60°
- Vertical (up/down) tilt: ±30°
Configurable minimum face size of 20 - 40 pixels
Configurable region of interest in the input frame
Configurable start position in the input frame
Supports up to 35 face detections in a single frame
Interrupt generation to ARM using the Video Processing Subsystem (VPSS) multiplexed interrupt mechanism
Robust performance in low light conditions, night vision, monochromatic, and false color sensing as skin tone not used for face detection
Supported input size is (256X192)
Input format is 8-bit gray scale data

The Face Detection Module register memory mapping (offsets) is shown in Table 7-44.

Table 7-44 Face Detection Module Registers

Offset	Acronym	Register Description
0x000	FDIF_PID	FDIF PID
0x008	FDIF_INTEN	FDIF Interrupt enable
0x00C	FDIF_PICADDR	FDIF Picture Data address
0x010	FDIF_WKADDR	FDIF Work Area address
0x020	FD_CTRL	FD Core Control Register
0x024	FD_DNUM	Detect number
0x028	FD_DCOND	Detect Condition set register
0x02C	FD_STARTX	X Start address
0x030	FD_STARTY	Y Start address
0x034	FD_SIZEX	X Size for detection
0x038	FD_SIZEY	Y Size for detection
0x03C	FD_LHIT	Detect process threshold
0x100	FD_CENTERX1	Detect Result Center X Address
0x104	FD_CENTERY1	Detect Result Center Y Address
0x108	FD_CONFSIZE1	Detect Result Confidence/Size
0x10C	FD_ANGLE1	Detect Angle
0x110	FD_CENTERX2	Detect Result Center X Address
0x114	FD_CENTERY2	Detect Result Center Y Address
0x118	FD_CONFSIZE2	Detect Result Confidence/Size
0x11C	FD_ANGLE2	Detect Angle
0x120	FD_CENTERX3	Detect Result Center X Address
0x124	FD_CENTERY3	Detect Result Center Y Address
0x128	FD_CONFSIZE3	Detect Result Confidence/Size
0x12C	FD_ANGLE3	Detect Angle
0x130	FD_CENTERX4	Detect Result Center X Address
0x134	FD_CENTERY4	Detect Result Center Y Address
0x138	FD_CONFSIZE4	Detect Result Confidence/Size
0x13C	FD_ANGLE4	Detect Angle
0x140	FD_CENTERX5	Detect Result Center X Address
0x144	FD_CENTERY5	Detect Result Center Y Address
0x148	FD_CONFSIZE5	Detect Result Confidence/Size
0x14C	FD_ANGLE5	Detect Angle
0x150	FD_CENTERX6	Detect Result Center X Address
0x154	FD_CENTERY6	Detect Result Center Y Address
0x158	FD_CONFSIZE6	Detect Result Confidence/Size
0x15C	FD_ANGLE6	Detect Angle
0x160	FD_CENTERX7	Detect Result Center X Address
0x164	FD_CENTERY7	Detect Result Center Y Address
0x168	FD_CONFSIZE7	Detect Result Confidence/Size
0x16C	FD_ANGLE7	Detect Angle
0x170	FD_CENTERX8	Detect Result Center X Address
0x174	FD_CENTERY8	Detect Result Center Y Address
0x178	FD_CONFSIZE8	Detect Result Confidence/Size
0x17C	FD_ANGLE8	Detect Angle
0x180	FD_CENTERX9	Detect Result Center X Address
0x184	FD_CENTERY9	Detect Result Center Y Address
0x188	FD_CONFSIZE9	Detect Result Confidence/Size
0x18C	FD_ANGLE9	Detect Angle
0x190	FD_CENTERX10	Detect Result Center X Address
0x194	FD_CENTERY10	Detect Result Center Y Address
0x198	FD_CONFSIZE10	Detect Result Confidence/Size
0x19C	FD_ANGLE10	Detect Angle
0x1A0	FD_CENTERX11	Detect Result Center X Address
0x1A4	FD_CENTERY11	Detect Result Center Y Address
0x1A8	FD_CONFSIZE11	Detect Result Confidence/Size
0x1AC	FD_ANGLE11	Detect Angle
0x1B0	FD_CENTERX12	Detect Result Center X Address
0x1B4	FD_CENTERY12	Detect Result Center Y Address
0x1B8	FD_CONFSIZE12	Detect Result Confidence/Size
0x1BC	FD_ANGLE12	Detect Angle
0x1C0	FD_CENTERX13	Detect Result Center X Address
0x1C4	FD_CENTERY13	Detect Result Center Y Address
0x1C8	FD_CONFSIZE13	Detect Result Confidence/Size
0x1CC	FD_ANGLE13	Detect Angle
0x1D0	FD_CENTERX14	Detect Result Center X Address
0x1D4	FD_CENTERY14	Detect Result Center Y Address
0x1D8	FD_CONFSIZE14	Detect Result Confidence/Size
0x1DC	FD_ANGLE14	Detect Angle
0x1E0	FD_CENTERX15	Detect Result Center X Address
0x1E4	FD_CENTERY15	Detect Result Center Y Address
0x1E8	FD_CONFSIZE15	Detect Result Confidence/Size
0x1EC	FD_ANGLE15	Detect Angle
0x1F0	FD_CENTERX16	Detect Result Center X Address
0x1F4	FD_CENTERY16	Detect Result Center Y Address
0x1F8	FD_CONFSIZE16	Detect Result Confidence/Size
0x1FC	FD_ANGLE16	Detect Angle
0x200	FD_CENTERX17	Detect Result Center X Address
0x204	FD_CENTERY17	Detect Result Center Y Address
0x208	FD_CONFSIZE17	Detect Result Confidence/Size
0x20C	FD_ANGLE17	Detect Angle
0x210	FD_CENTERX18	Detect Result Center X Address
0x214	FD_CENTERY18	Detect Result Center Y Address
0x218	FD_CONFSIZE18	Detect Result Confidence/Size
0x21C	FD_ANGLE18	Detect Angle
0x220	FD_CENTERX19	Detect Result Center X Address
0x224	FD_CENTERY19	Detect Result Center Y Address
0x228	FD_CONFSIZE19	Detect Result Confidence/Size
0x22C	FD_ANGLE19	Detect Angle
0x230	FD_CENTERX20	Detect Result Center X Address
0x234	FD_CENTERY20	Detect Result Center Y Address
0x238	FD_CONFSIZE20	Detect Result Confidence/Size
0x23C	FD_ANGLE20	Detect Angle
0x240	FD_CENTERX21	Detect Result Center X Address
0x244	FD_CENTERY21	Detect Result Center Y Address
0x248	FD_CONFSIZE21	Detect Result Confidence/Size
0x24C	FD_ANGLE21	Detect Angle
0x250	FD_CENTERX22	Detect Result Center X Address
0x254	FD_CENTERY22	Detect Result Center Y Address
0x258	FD_CONFSIZE22	Detect Result Confidence/Size
0x25C	FD_ANGLE22	Detect Angle
0x260	FD_CENTERX23	Detect Result Center X Address
0x264	FD_CENTERY23	Detect Result Center Y Address
0x268	FD_CONFSIZE23	Detect Result Confidence/Size
0x26C	FD_ANGLE23	Detect Angle
0x270	FD_CENTERX24	Detect Result Center X Address
0x274	FD_CENTERY24	Detect Result Center Y Address
0x278	FD_CONFSIZE24	Detect Result Confidence/Size
0x27C	FD_ANGLE24	Detect Angle
0x280	FD_CENTERX25	Detect Result Center X Address
0x284	FD_CENTERY25	Detect Result Center Y Address
0x288	FD_CONFSIZE25	Detect Result Confidence/Size
0x28C	FD_ANGLE25	Detect Angle
0x290	FD_CENTERX26	Detect Result Center X Address
0x294	FD_CENTERY26	Detect Result Center Y Address
0x298	FD_CONFSIZE26	Detect Result Confidence/Size
0x29C	FD_ANGLE26	Detect Angle
0x2A0	FD_CENTERX27	Detect Result Center X Address
0x2A4	FD_CENTERY27	Detect Result Center Y Address
0x2A8	FD_CONFSIZE27	Detect Result Confidence/Size
0x2AC	FD_ANGLE27	Detect Angle
0x2B0	FD_CENTERX28	Detect Result Center X Address
0x2B4	FD_CENTERY28	Detect Result Center Y Address
0x2B8	FD_CONFSIZE28	Detect Result Confidence/Size
0x2BC	FD_ANGLE28	Detect Angle
0x2C0	FD_CENTERX29	Detect Result Center X Address
0x2C4	FD_CENTERY29	Detect Result Center Y Address
0x2C8	FD_CONFSIZE29	Detect Result Confidence/Size
0x2CC	FD_ANGLE29	Detect Angle
0x2D0	FD_CENTERX30	Detect Result Center X Address
0x2D4	FD_CENTERY30	Detect Result Center Y Address
0x2D8	FD_CONFSIZE30	Detect Result Confidence/Size
0x2DC	FD_ANGLE30	Detect Angle
0x2E0	FD_CENTERX31	Detect Result Center X Address
0x2E4	FD_CENTERY31	Detect Result Center Y Address
0x2E8	FD_CONFSIZE31	Detect Result Confidence/Size
0x2EC	FD_ANGLE31	Detect Angle
0x2F0	FD_CENTERX32	Detect Result Center X Address
0x2F4	FD_CENTERY32	Detect Result Center Y Address
0x2F8	FD_CONFSIZE32	Detect Result Confidence/Size
0x2FC	FD_ANGLE32	Detect Angle
0x300	FD_CENTERX33	Detect Result Center X Address
0x304	FD_CENTERY33	Detect Result Center Y Address
0x308	FD_CONFSIZE33	Detect Result Confidence/Size
0x30C	FD_ANGLE33	Detect Angle
0x310	FD_CENTERX34	Detect Result Center X Address
0x314	FD_CENTERY34	Detect Result Center Y Address
0x318	FD_CONFSIZE34	Detect Result Confidence/Size
0x31C	FD_ANGLE34	Detect Angle
0x320	FD_CENTERX35	Detect Result Center X Address
0x324	FD_CENTERY35	Detect Result Center Y Address
0x328	FD_CONFSIZE35	Detect Result Confidence/Size
0x32C	FD_ANGLE35	Detect Angle

7.12.1.6 VPFE Electrical Data/Timing

Table 7-45 Timing Requirements for VPFE PCLK Master/Slave Mode⁽¹⁾ (see Figure 7-31)

NO.				MIN	MAX	UNIT
1	t_c(PCLK)	Cycle time, PCLK	Slave Mode	8.33	120	ns
1	t_c(PCLK)	Cycle time, PCLK	Master Mode	13.33	120	ns
2	t_w(PCLKH)	Pulse duration, PCLK high		tc(PCLK)* 0.35	tc(PCLK)* 0.65	ns
3	t_w(PCLKL)	Pulse duration, PCLK low		tc(PCLK)* 0.35	tc(PCLK)* 0.65	ns
4	t_t(PCLK)	Transition time, PCLK			2	ns

(1) P = 1/SYSCLK4 in nanoseconds (ns). For example, if the SYSCLK4 frequency is 135 MHz, use P = 7.41 ns. See Section 4.3, Device Clocking, for more information on the supported clock configurations of the device.

Figure 7-31 VPFE PCLK Timing

Table 7-46 Timing Requirements for VPFE (ISIF) Slave Mode (see Figure 7-32)

NO.				DEVICE		UNIT
NO.				MIN	MAX	UNIT
5	t_{su(DATAV-PCLK)}	Setup time, ISIF DATA valid before PCLK edge	Positive Edge	2.5		ns
5	t_{su(DATAV-PCLK)}	Setup time, ISIF DATA valid before PCLK edge	Negative Edge	1.5		ns
6	t_{h(PCLK-DATAV)}	Hold time, ISIF DATA valid after PCLK edge	Positive Edge	1.5		ns
6	t_{h(PCLK-DATAV)}	Hold time, ISIF DATA valid after PCLK edge	Negative Edge	2.5		ns
7	t_su(HDV-PCLK)	Setup time, HD valid before PCLK edge	Positive Edge	2.5		ns
7	t_su(HDV-PCLK)	Setup time, HD valid before PCLK edge	Negative Edge	1.5		ns
8	t_h(PCLK-HDV)	Hold time, HD valid after PCLK edge	Positive Edge	1.5		ns
8	t_h(PCLK-HDV)	Hold time, HD valid after PCLK edge	Negative Edge	2.5		ns
9	t_su(VDV-PCLK)	Setup time, VD valid before PCLK edge	Positive Edge	2.5		ns
9	t_su(VDV-PCLK)	Setup time, VD valid before PCLK edge	Negative Edge	1.5		ns
10	t_h(PCLK-VDV)	Hold time, VD valid after PCLK edge	Positive Edge	1.5		ns
10	t_h(PCLK-VDV)	Hold time, VD valid after PCLK edge	Negative Edge	2.5		ns
11	t_{su(C_WEV-PCLK)}	Setup time, C_WE valid before PCLK edge	Positive Edge	2.5		ns
11	t_{su(C_WEV-PCLK)}	Setup time, C_WE valid before PCLK edge	Negative Edge	1.5		ns
12	t_{h(PCLK-C_WEV)}	Hold time, C_WE valid after PCLK edge	Positive Edge	1.5		ns
12	t_{h(PCLK-C_WEV)}	Hold time, C_WE valid after PCLK edge	Negative Edge	2.5		ns
13	t_{su(C_FIELDV-PCLK)}	Setup time, C_FIELD valid before PCLK edge	Positive Edge	2.5		ns
13	t_{su(C_FIELDV-PCLK)}	Setup time, C_FIELD valid before PCLK edge	Negative Edge	1.5		ns
14	t_{h(PCLK-C_FIELDV)}	Hold time, C_FIELD valid after PCLK edge	Positive Edge	1.5		ns
14	t_{h(PCLK-C_FIELDV)}	Hold time, C_FIELD valid after PCLK edge	Negative Edge	2.5		ns

TMS320DM369 td_vpfeslaveupdated_prs348.gif

Figure 7-32 VPFE (ISIF) Slave Mode Input Data Timing

Table 7-47 Timing Requirements for VPFE (ISIF) Master Mode⁽¹⁾ (see Figure 7-33)

NO.				DEVICE		UNIT
NO.				MIN	MAX	UNIT
15	t_{su(DATAV-PCLK)}	Setup time, ISIF DATA valid before PCLK edge	Positive Edge	2.5		ns
15	t_{su(DATAV-PCLK)}	Setup time, ISIF DATA valid before PCLK edge	Negative Edge	1.5		ns
16	t_{h(PCLK-DATAV)}	Hold time, ISIF DATA valid after PCLK edge	Positive Edge	1.5		ns
16	t_{h(PCLK-DATAV)}	Hold time, ISIF DATA valid after PCLK edge	Negative Edge	2.5		ns
23	t_{su(CWEV-PCLK)}	Setup time, C_WE valid before PCLK edge	Positive Edge	2.5		ns
23	t_{su(CWEV-PCLK)}	Setup time, C_WE valid before PCLK edge	Negative Edge	1.5		ns
24	t_h(PCLK-CWEV)	Hold time, C_WE valid after PCLK edge	Positive Edge	1.5		ns
24	t_h(PCLK-CWEV)	Hold time, C_WE valid after PCLK edge	Negative Edge	2.5		ns

(1) The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced.

TMS320DM369 td_vpfemstriupdated_prs348.gif

Figure 7-33 VPFE (ISIF) Master Mode Input Data Timing

Table 7-48 Switching Characteristics Over Recommended Operating Conditions for VPFE (ISIF) Master Mode (see Figure 7-34)

NO.	PARAMETER		DEVICE		UNIT
NO.	PARAMETER		MIN	MAX	UNIT
18	t_{d(PCLKL-HDIV)}	Delay time, PCLK edge to HD valid	1.5	11	ns
20	t_{d(PCLKL-VDIV)}	Delay time, PCLK edge to VD valid	1.5	11	ns

Figure 7-34 VPFE (ISIF) Master Mode Control Output Data Timing

7.12.2 Video Processing Back-End (VPBE)

The Video Processing Back-End of VPBE module is comprised of the On Screen Display (OSD) module and the Video Encoder / Digital LCD Controller (VENC/DLCD).

Table 7-49 lists the Video Processing Back-End (VPBE) module registers, their corresponding acronyms, and the device memory locations (offsets).

Table 7-49 VPBE Module Register Map

Address	Peripheral	Description
0x01C7:0200	VPBE_CLK_CTRL	VPBE Clock Control
0x01C7:1C00	OSD	VPBE On-Screen Display
0x01C7:1E00	VENC	VPBE Video Encoder

7.12.2.1 On-Screen Display (OSD)

The primary function of the OSD module is to gather and blend video data and display/bitmap data and then pass it to the Video Encoder (VENC) in YCbCr format. The video and display data is read from external DDR2/mDDR memory. The OSD is programmed via control and parameter registers. The following are the primary features that are supported by the OSD.

Support for two video windows and two OSD bitmapped windows that can be displayed simultaneously (VIDWIN0/VIDWIN1 and OSDWIN0/OSDWIN1).
Video windows support YCbCr data in 422 and 420 formats from external memory, with the ability to interchange the order of the CbCr component in the 32-bit word
OSD bitmap windows support = 4/8 bit width index data of color palette
In addition one OSD bitmap window at a time can be configured to one of the following:
- YUV422 (same as video data)
- RGB format data in 16-bit mode (R=5bit, G=6bit, B=5bit)
- 24-bit mode (each R/G/B=8bit) with pixel level blending with video windows
Programmable color palette with the ability to select between a RAM/ROM table with support for 256 colors.
Support for 2 ROM tables, one of which can be selected at a given time
Separate enable/disable control for each window
Programmable width, height, and base starting coordinates for each window
External memory address and offset registers for each window
Support for x2 and x4 zoom in both the horizontal and vertical direction
Pixel-level blending/transparency/blinking attributes can be defined for OSDWIN0 when OSDWIN1 is configured as an attribute window for OSDWIN0.
Support for blinking intervals to the attribute window
Ability to select either field/frame mode for the windows (interlaced/progressive)
An eight step blending process between the bitmap and video windows
Transparency support for the bitmap and video data (when a bitmap pixel is zero, there will be no blending for that corresponding video pixel)
Ability to resize from VGA to NTSC/PAL (640x480 to 720x576) for both the OSD and video windows
Horizontal rescaling x1.5 is supported
Support for a rectangular cursor window and a programmable background color selection.
The width, height, and color of the cursor is selectable
The display priority is: Rectangular-Cursor > OSDWIN1 > OSDWIN0 > VIDWIN1 > VIDWIN0 > background color
Support for attenuation of the YCbCr values for the REC601 standard.

The following restrictions exist in the OSD module.

If the vertical resize filter is enabled for either of the video windows, the maximum horizontal window dimension cannot be greater than 1024 currently. This is due to the limitation in the size of the line memory.
It is not possible to use both of the CLUT ROMs at the same time. However, a window can use RAM while another uses ROM.

Table 7-50 lists the On-Screen Display (OSD) registers, their corresponding acronyms, and the device memory locations (offsets).

Table 7-50 On-Screen Display (OSD) Registers

Offset	Acronym	Register Description
0h	MODE	OSD Mode Setup
4h	VIDWINMD	Video Window Mode Setup
8h	OSDWIN0MD	Bitmap Window 0 Mode Setup
Ch	OSDWIN1MD	OSD Window 1 Mode Setup (when used as a second OSD window)
Ch	OSDATRMD	OSD Attribute Window Mode Setup (when used as an attribute window)
10h	RECTCUR	Rectangular Cursor Setup
14h	RSV0	Reserved
18h	VIDWIN0OFST	Video Window 0 Offset
1Ch	VIDWIN1OFST	Video Window 1 Offset
20h	OSDWIN0OFST	Bitmap Window 0 Offset
24h	OSDWIN1OFST	Bitmap Window 1/Attribute Window Offset
28h	VIDWINADH	Video Window 0/1 Address - High
2Ch	VIDWIN0ADL	Video Window 0 Address - Low
30h	VIDWIN1ADL	Video Window 1 Address - Low
34h	OSDWINADH	BMP Window 0/1 Address - High
38h	OSDWIN0ADL	BMP Window 0 Address - Low
3Ch	OSDWIN1ADL	Bitmap Window 1/Attribute Address - Low
40h	BASEPX	Base Pixel X
44h	BASEPY	Base Pixel Y
48h	VIDWIN0XP	Video Window 0 X-Position
4Ch	VIDWIN0YP	Video Window 0 Y-Position
50h	VIDWIN0XL	Video Window 0 X-Size
54h	VIDWIN0YL	Video Window 0 Y-Size
58h	VIDWIN1XP	Video Window 1 X-Position
5Ch	VIDWIN1YP	Video Window 1 Y-Position
60h	VIDWIN1XL	Video Window 1 X-Size
64h	VIDWIN1YL	Video Window 1 Y-Size
68h	OSDWIN0XP	Bitmap Window 0 X-Position
6Ch	OSDWIN0YP	Bitmap Window 0 Y-Position
70h	OSDWIN0XL	Bitmap Window 0 X-Size
74h	OSDWIN0YL	Bitmap Window 0 Y-Size
78h	OSDWIN1XP	Bitmap Window 1 X-Position
7Ch	OSDWIN1YP	Bitmap Window 1 Y-Position
80h	OSDWIN1XL	Bitmap Window 1 X-Size
84h	OSDWIN1YL	Bitmap Window 1 Y-Size
88h	CURXP	Rectangular Cursor Window X-Position
8Ch	CURYP	Rectangular Cursor Window Y-Position
90h	CURXL	Rectangular Cursor Window X-Size
94h	CURYL	Rectangular Cursor Window Y-Size
98h	RSV1	Reserved
9Ch	RSV2	Reserved
A0h	W0BMP01	Window 0 Bitmap Value to Palette Map 0/1
A4h	W0BMP23	Window 0 Bitmap Value to Palette Map 2/3
A8h	W0BMP45	Window 0 Bitmap Value to Palette Map 4/5
ACh	W0BMP67	Window 0 Bitmap Value to Palette Map 6/7
B0h	W0BMP89	Window 0 Bitmap Value to Palette Map 8/9
B4h	W0BMPAB	Window 0 Bitmap Value to Palette Map A/B
B8h	W0BMPCD	Window 0 Bitmap Value to Palette Map C/D
BCh	W0BMPEF	Window 0 Bitmap Value to Palette Map E/F
C0h	W1BMP01	Window 1 Bitmap Value to Palette Map 0/1
C4h	W1BMP23	Window 1 Bitmap Value to Palette Map 2/3
C8h	W1BMP45	Window 1 Bitmap Value to Palette Map 4/5
CCh	W1BMP67	Window 1 Bitmap Value to Palette Map 6/7
D0h	W1BMP89	Window 1 Bitmap Value to Palette Map 8/9
D4h	W1BMPAB	Window 1 Bitmap Value to Palette Map A/B
D8h	W1BMPCD	Window 1 Bitmap Value to Palette Map C/D
DCh	W1BMPEF	Window 1 Bitmap Value to Palette Map E/F
E0h	VBNDRY	Test Mode
E4h	EXTMODE	Extended Mode
E8h	MISCCTL	Miscellaneous Control
ECh	CLUTRAMYCB	CLUT RAM Y/Cb Setup
F0h	CLUTRAMCR	CLUT RAM Cr/Mapping Setup
F4h	TRANSPVALL	Transparent Color Code - Lower
F8h	TRANSPVALU	Transparent Color Code - Upper
FCh	TRANSPBMPIDX	Transparent Index Code for Bitmaps

7.12.2.2 Video Encoder / Digital LCD Controller (VENC/DLCD)

The VENC/DLCD consists of three major blocks:

Video encoder to generate analog video output
Digital LCD controller to generate digital RGB/YCbCr data output and timing signals
Timing generator

The video encoder for analog video supports the following features:

Master Clock Input - 27 MHz or 74.25 MHz
SDTV Support
- Composite NTSC-M, PAL-B/D/G/H/I
- S-Video (Y/C)
- Component YPbPr
- RGB
- CGMS/WSS
- Closed Caption
HDTV Support
- 525p/625p/720p/1080i
- Component YPbPr
- RGB
- CGMS/WSS
Master/Slave Operation
Three 10-bit D/A Converters

The digital LCD controller supports the following features:

Programmable Timing Generator
Various Output Formats
- YCbCr 4:2:2 16-bit
- YCbCr 4:2:2 8-bit
- Parallel RGB 16/18/24-bit
- Serial RGB 8-bit
EAV/SAV insertion
Master/Slave Operation

Table 7-51 lists the Video Encoder / Digital LCD Controller (VENC/DLCD) registers, their corresponding acronyms, and the device memory locations (offsets).

Table 7-51 Video Encoder (VENC) Registers

Offset	Acronym	Register Description
0h	VMOD	Video Mode
4h	VIOCTL	Video Interface I/O Control
8h	VDPRO	Video Data Processing
Ch	SYNCCTL	Sync Control
10h	HSPLS	Horizontal Sync Pulse Width
14h	VSPLS	Vertical Sync Pulse Width
18h	HINTVL	Horizontal Interval
1Ch	HSTART	Horizontal Valid Data Start Position
20h	HVALID	Horizontal Data Valid Range
24h	VINTVL	Vertical Interval
28h	VSTART	Vertical Valid Data Start Position
2Ch	VVALID	Vertical Data Valid Range
30h	HSDLY	Horizontal Sync Delay
34h	VSDLY	Vertical Sync Delay
38h	YCCCTL	YCbCr Control
3Ch	RGBCTL	RGB Control
40h	RGBCLP	RGB Level Clipping
44h	LINECTL	Line ID Control
48h	CULLLINE	Culling Line Control
4Ch	LCDOUT	LCD Output Signal Control
50h	BRT0	Brightness Start Position Signal Control
54h	BRT1	Brightness Width Signal Control
58h	ACCTL	LCD_AC Signal Control
5Ch	PWM0	PWM Output Period
60h	PWM1	PWM Output Pulse Width
64h	DCLKCTL	DCLK Control
68h	DCLKPTN0	DCLK Pattern 0
6Ch	DCLKPTN1	DCLK Pattern 1
70h	DCLKPTN2	DCLK Pattern 2
74h	DCLKPTN3	DCLK Pattern 3
78h	DCLKPTN0A	DCLK Auxiliary Pattern 0
7Ch	DCLKPTN1A	DCLK Auxiliary Pattern 1
80h	DCLKPTN2A	DCLK Auxiliary Pattern 2
84h	DCLKPTN3A	DCLK Auxiliary Pattern 3
88h	DCLKHSTT	Horizontal DCLK Mask Start Position
8Ch	DCLKHSTTA	Horizontal Auxiliary DCLK Mask Start Position
90h	DCLKHVLD	Horizontal DCLK Mask Range
94h	DCLKVSTT	Vertical DCLK Mask Start Position
98h	DCLKVVLD	Vertical DCLK Mask Range
9Ch	CAPCTL	Closed Caption Control
A0h	CAPDO	Closed Caption Odd Field Data
A4h	CAPDE	Closed Caption Even Field Data
A8h	ATR0	Video Attribute Data 0
ACh	ATR1	Video Attribute Data 1
B0h	ATR2	Video Attribute Data 2
B4h	RSV0	Reserved 0
B8h	VSTAT	Video Status
BCh	RAMADR	GCP/FRC Table RAM Address
C0h	RAMPORT	GCP/FRC Table RAM Data Port
C4h	DACTST	DAC Test
C8h	YCOLVL	YOUT and COUT Levels
CCh	SCPROG	Sub-Carrier Programming
D0h	RSV1	Reserved 1
D4h	RSV2	Reserved 2
D8h	RSV3	Reserved 3
DCh	CVBS	Composite Mode
E0h	CMPNT	Component Mode
E4h	ETMG0	CVBS Timing Control 0
E8h	ETMG1	CVBS Timing Control 1
ECh	ETMG2	CVBS Timing Control 2
F0h	ETMG3	CVBS Timing Control 3
F4h	DACSEL	DAC Output Select
100h	ARGBX0	Analog RGB Matrix 0
104h	ARGBX1	Analog RGB Matrix 1
108h	ARGBX2	Analog RGB Matrix 2
10Ch	ARGBX3	Analog RGB Matrix 3
110h	ARGBX4	Analog RGB Matrix 4
114h	DRGBX0	Digital RGB Matrix 0
118h	DRGBX1	Digital RGB Matrix 1
11Ch	DRGBX2	Digital RGB Matrix 2
120h	DRGBX3	Digital RGB Matrix 3
124h	DRGBX4	Digital RGB Matrix 4
128h	VSTARTA	Vertical Data Valid Start Position For Even Field
12Ch	OSDCLK0	OSD Clock Control 0
130h	OSDCLK1	OSD Clock Control 1
134h	HVLDCL0	Horizontal Valid Culling Control 0
138h	HVLDCL1	Horizontal Valid Culling Control 1
13Ch	OSDHADV	OSD Horizontal Sync Advance
140h	CLKCTL	Clock Control
144h	GAMCTL	Enable Gamma Correction
148h	VVALIDA	Vertical Data Valid Area For Even Field
14Ch	BATR0	Video Attribute 0 For Type B Packet
150h	BATR1	Video Attribute 1 For Type B Packet
154h	BATR2	Video Attribute 2 For Type B Packet
158h	BATR3	Video Attribute 3 For Type B Packet
15Ch	BATR4	Video Attribute 4 For Type B Packet
160h	BATR5	Video Attribute 5 For Type B Packet
164h	BATR6	Video Attribute 6 For Type B Packet
168h	BATR7	Video Attribute 7 For Type B Packet
16Ch	BATR8	Video Attribute 8 For Type B Packet
170h	DACAMP	Gain and Offset

7.12.2.3 VPBE Electrical Data/Timing

Table 7-52 Timing Requirements for VPBE CLK Inputs (see Figure 7-35)

NO.			DEVICE		UNIT
NO.			MIN	MAX	UNIT
1	t_c(PCLK)	Cycle time, PCLK⁽¹⁾	13.33	160	ns
2	t_w(PCLKH)	Pulse duration, PCLK high	5.7		ns
3	t_w(PCLKL)	Pulse duration, PCLK low	5.7		ns
4	t_t(PCLK)	Transition time, PCLK		3	ns
5	t_c(EXTCLK)	Cycle time, EXTCLK	13.33	160	ns
6	t_w(EXTCLKH)	Pulse duration, EXTCLK high	5.7		ns
7	t_w(EXTCLKL)	Pulse duration, EXTCLK low	5.7		ns
8	t_t(EXTCLK)	Transition time, EXTCLK		3	ns

(1) For timing specifications relating to PCLK see Table 7-45, Timing Requirements for VPFE PCLK Master/Slave Mode.

Figure 7-35 VPBE PCLK and EXTCLK Timing

Table 7-53 Timing Requirements for VPBE Control Input With Respect to PCLK and EXTCLK⁽¹⁾ ⁽³⁾ ⁽²⁾ (see Figure 7-36)

NO.				DEVICE		UNIT
NO.				MIN	MAX	UNIT
9	t_{su(VCTLV-VCLKIN)}	Setup time, VCTL valid before VCLKIN edge	Positive Edge	4		ns
9	t_{su(VCTLV-VCLKIN)}	Setup time, VCTL valid before VCLKIN edge	Negative Edge	3		ns
10	t_{h(VCLKIN-VCTLV)}	Hold time, VCTL valid after VCLKIN edge	Positive Edge	1		ns
10	t_{h(VCLKIN-VCTLV)}	Hold time, VCTL valid after VCLKIN edge	Negative Edge	2		ns

(1) The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising edge of VCLKIN is referenced. When in negative edge clocking mode, the falling edge of VCLKIN is referenced.

(2) VCLKIN = PCLK or EXTCLK. Positive and Negative Edge apply to PCLK only; EXTCLK does not support Negative Edge clocking.

(3) VCTL = HSYNC, VSYNC, and FIELD

TMS320DM369 td_vpbeinck2_prs348_updated.gif

Figure 7-36 VPBE Input Timing With Respect to PCLK and EXTCLK

Table 7-54 Switching Characteristics Over Recommended Operating Conditions for VPBE Control and Data Output With Respect to PCLK and EXTCLK⁽¹⁾ ⁽²⁾ ⁽³⁾ (see Figure 7-37)

NO.	PARAMETER			DEVICE		UNIT
NO.	PARAMETER			MIN	MAX	UNIT
11	t_{d(VCLKIN-VCTLV)}	Delay time, VCLKIN edge to VCTL valid	Positive Edge		15	ns
11	t_{d(VCLKIN-VCTLV)}	Delay time, VCLKIN edge to VCTL valid	Negative Edge		16	ns
12	t_{d(VCLKIN-VCTLIV)}	Delay time, VCLKIN edge to VCTL invalid		2		ns
13	t_{d(VCLKIN-VDATAV)}	Delay time, VCLKIN edge to VDATA valid	VCLKIN = EXTCLK		15	ns
13	t_{d(VCLKIN-VDATAV)}	Delay time, VCLKIN edge to VDATA valid	VCLKIN = PCLK		17.5	ns
14	t_{d(VCLKIN-VDATAIV)}	Delay time, VCLKIN edge to VDATA invalid		2		ns

(2) VCLKIN = PCLK or EXTCLK. Positive and Negative Edge apply to PCLK only; EXTCLK does not support Negative Edge clocking.

(3) VCTL = HSYNC, VSYNC, FIELD, and LCD_OE.

TMS320DM369 td_vpbeotcks_prs348_updated2.gif

Figure 7-37 VPBE Control and Data Output With Respect to PCLK and EXTCLK

Table 7-55 Switching Characteristics Over Recommended Operating Conditions for VPBE Control and Data Output With Respect to VCLK⁽¹⁾ ⁽²⁾ ⁽³⁾(see Figure 7-38)

NO.	PARAMETER		DEVICE		UNIT
NO.	PARAMETER		MIN	MAX	UNIT
17	t_c(VCLK)	Cycle time, VCLK	13.33	160	ns
18	t_w(VCLKH)	Pulse duration, VCLK high	5.7		ns
19	t_w(VCLKL)	Pulse duration, VCLK low	5.7		ns
20	t_t(VCLK)	Transition time, VCLK		3	ns
21	t_{d(VCLKINH-VCLKH)}	Delay time, VCLKIN high to VCLK high	3	16	ns
22	t_{d(VCLKINL-VCLKL)}	Delay time, VCLKIN low to VCLK low	3	16	ns
23	t_{d(VCLK-VCTLV)}	Delay time, VCLK edge to VCTL valid		1.5	ns
24	t_{d(VCLK-VCTLIV)}	Delay time, VCLK edge to VCTL invalid	-1.5		ns
25	t_{d(VCLK-VDATAV)}	Delay time, VCLK edge to VDATA valid		1.5	ns
26	t_{d(VCLK-VDATAIV)}	Delay time, VCLK edge to VDATA invalid	-1.5		ns

(1) The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising edge of VCLK is referenced. When in negative edge clocking mode, the falling edge of VCLK is referenced.

(2) VCLKIN = PCLK or EXTCLK. Positive and Negative edge apply for PCLK only, EXTCLK does not support negative edge clocking. For timing specifications relating to PCLK, see Table 7-45, Timing Requirements for VPFE PCLK Master/Slave Mode.

(3) VCTL= HSYNC, VSYNC, FIELD and LCD_OE.

TMS320DM369 td_vpbeovclk_prs348_updated2.gif

Figure 7-38 VPBE Control and Data Output Timing With Respect to VCLK

7.12.2.4 High-Definition (HD) DACs and Video Buffer Electrical Data/Timing

Three DACs and a video buffer are available on the device.

7.12.2.4.1 HD DACs-Only Option

In the HD DACs-only configuration, the internal video buffer is not used and an external video buffer is attached to the DACs. Another solution is to use a Video Amplifier, such as the Texas Instruments' THS7303 which provides a complete solution to the typical output circuit shown in Figure 7-39.

TMS320DM369 daclowpassfilterupdated_prs457_525454.gif

A. RBIAS = 2400Ω.

B. VREF = 0.5V (from external supply).

C. IDACOUT must be connected to V_ss or left open for proper device configuration.

D. VFB must be connected to V_ss or left open for proper device configuration.

E. TVOUT must be connected to V_ss or left open for proper device configuration.

Figure 7-39 HD Video DAC Application Example

7.12.2.4.2 DAC With Video Buffer Option

In a DAC plus video buffer configuration, one of the DACs may be used along with the video buffer for standard definition TVOUT mode. In the DAC plus video buffer configuration, the DAC and internal video buffer are both used, and a TV cable may be attached directly to the output of the video buffer. Figure 7-40 shows an example of the DAC Plus Video Buffer Option circuit configuration.

TMS320DM369 dacvideobuffer_prs457_updated.gif

Figure 7-40 SD Video Buffer Application Example

7.13 USB2.0

The USB2.0 peripheral supports the following features:

USB 2.0 peripheral at speeds high speed (HS: 480 Mbps) and full speed (FS: 12 Mbps)
USB 2.0 host at speeds HS, FS, and low speed (LS: 1.5 Mbps)
All transfer modes (control, bulk, interrupt, and isochronous)
Four Transmit (TX) and four Receive (RX) endpoints in addition to endpoint 0
FIFO RAM
- 4K bytes shared by all endpoints.
- Programmable FIFO size
Includes a DMA sub-module that supports four TX and four RX channels of CPPI 3.0 DMAs
RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB
USB OTG extensions, i.e. session request protocol (SRP) and host negotiation protocol (HNP)

The USB2.0 peripheral does not support the following features:

On-chip charge pump
High bandwidth ISO mode is not supported (triple buffering)
RNDIS mode acceleration for USB sizes that are not multiples of 64 bytes
Endpoint max USB packet sizes that do not conform to the USB 2.0 spec (for FS/LS: 8, 16, 32, 64, and 1023 are defined; for HS: 64, 128, 512, and 1024 are defined)

7.13.1 USB Peripheral Register Description

Table 7-56 lists the USB registers, their corresponding acronyms, and the device memory locations (offsets).

Table 7-56 Universal Serial Bus (USB) Registers

Offset	Acronym	Register Description
4h	CTRLR	Control Register
8h	STATR	Status Register
10h	RNDISR	RNDIS Register
14h	AUTOREQ	Autorequest Register
20h	INTSRCR	USB Interrupt Source Register
24h	INTSETR	USB Interrupt Source Set Register
28h	INTCLRR	USB Interrupt Source Clear Register
2Ch	INTMSKR	USB Interrupt Mask Register
30h	INTMSKSETR	USB Interrupt Mask Set Register
34h	INTMSKCLRR	USB Interrupt Mask Clear Register
38h	INTMASKEDR	USB Interrupt Source Masked Register
3Ch	EOIR	USB End of Interrupt Register
40h	INTVECTR	USB Interrupt Vector Register
80h	TCPPICR	Transmit CPPI Control Register
84h	TCPPITDR	Transmit CPPI Teardown Register
88h	TCPPIEOIR	Transmit CPPI DMA Controller End of Interrupt Register
8Ch	Reserved	-
90h	TCPPIMSKSR	Transmit CPPI Masked Status Register
94h	TCPPIRAWSR	Transmit CPPI Raw Status Register
98h	TCPPIIENSETR	Transmit CPPI Interrupt Enable Set Register
9Ch	TCPPIIENCLRR	Transmit CPPI Interrupt Enable Clear Register
C0h	RCPPICR	Receive CPPI Control Register
D0h	RCPPIMSKSR	Receive CPPI Masked Status Register
D4h	RCPPIRAWSR	Receive CPPI Raw Status Register
D8h	RCPPIENSETR	Receive CPPI Interrupt Enable Set Register
DCh	RCPPIIENCLRR	Receive CPPI Interrupt Enable Clear Register
E0h	RBUFCNT0	Receive Buffer Count 0 Register
E4h	RBUFCNT1	Receive Buffer Count 1 Register
E8h	RBUFCNT2	Receive Buffer Count 2 Register
ECh	RBUFCNT3	Receive Buffer Count 3 Register
Transmit/Receive CPPI Channel 0 State Block
100h	TCPPIDMASTATEW0	Transmit CPPI DMA State Word 0
104h	TCPPIDMASTATEW1	Transmit CPPI DMA State Word 1
108h	TCPPIDMASTATEW2	Transmit CPPI DMA State Word 2
10Ch	TCPPIDMASTATEW3	Transmit CPPI DMA State Word 3
110h	TCPPIDMASTATEW4	Transmit CPPI DMA State Word 4
114h	TCPPIDMASTATEW5	Transmit CPPI DMA State Word 5
11Ch	TCPPICOMPPTR	Transmit CPPI Completion Pointer
120h	RCPPIDMASTATEW0	Receive CPPI DMA State Word 0
124h	RCPPIDMASTATEW1	Receive CPPI DMA State Word 1
128h	RCPPIDMASTATEW2	Receive CPPI DMA State Word 2
12Ch	RCPPIDMASTATEW3	Receive CPPI DMA State Word 3
130h	RCPPIDMASTATEW4	Receive CPPI DMA State Word 4
134h	RCPPIDMASTATEW5	Receive CPPI DMA State Word 5
138h	RCPPIDMASTATEW6	Receive CPPI DMA State Word 6
13Ch	RCPPICOMPPTR	Receive CPPI Completion Pointer
Transmit/Receive CPPI Channel 1 State Block
140h	TCPPIDMASTATEW0	Transmit CPPI DMA State Word 0
144h	TCPPIDMASTATEW1	Transmit CPPI DMA State Word 1
148h	TCPPIDMASTATEW2	Transmit CPPI DMA State Word 2
14Ch	TCPPIDMASTATEW3	Transmit CPPI DMA State Word 3
150h	TCPPIDMASTATEW4	Transmit CPPI DMA State Word 4
154h	TCPPIDMASTATEW5	Transmit CPPI DMA State Word 5
15Ch	TCPPICOMPPTR	Transmit CPPI Completion Pointer
160h	RCPPIDMASTATEW0	Receive CPPI DMA State Word 0
164h	RCPPIDMASTATEW1	Receive CPPI DMA State Word 1
168h	RCPPIDMASTATEW2	Receive CPPI DMA State Word 2
16Ch	RCPPIDMASTATEW3	Receive CPPI DMA State Word 3
170h	RCPPIDMASTATEW4	Receive CPPI DMA State Word 4
174h	RCPPIDMASTATEW5	Receive CPPI DMA State Word 5
178h	RCPPIDMASTATEW6	Receive CPPI DMA State Word 6
17Ch	RCPPICOMPPTR	Receive CPPI Completion Pointer
Transmit/Receive CPPI Channel 2 State Block
180h	TCPPIDMASTATEW0	Transmit CPPI DMA State Word 0
184h	TCPPIDMASTATEW1	Transmit CPPI DMA State Word 1
188h	TCPPIDMASTATEW2	Transmit CPPI DMA State Word 2
18Ch	TCPPIDMASTATEW3	Transmit CPPI DMA State Word 3
190h	TCPPIDMASTATEW4	Transmit CPPI DMA State Word 4
194h	TCPPIDMASTATEW5	Transmit CPPI DMA State Word 5
19Ch	TCPPICOMPPTR	Transmit CPPI Completion Pointer
1A0h	RCPPIDMASTATEW0	Receive CPPI DMA State Word 0
1A4h	RCPPIDMASTATEW1	Receive CPPI DMA State Word 1
1A8h	RCPPIDMASTATEW2	Receive CPPI DMA State Word 2
1ACh	RCPPIDMASTATEW3	Receive CPPI DMA State Word 3
1B0h	RCPPIDMASTATEW4	Receive CPPI DMA State Word 4
1B4h	RCPPIDMASTATEW5	Receive CPPI DMA State Word 5
1B8h	RCPPIDMASTATEW6	Receive CPPI DMA State Word 6
1BCh	RCPPICOMPPTR	Receive CPPI Completion Pointer
Transmit/Receive CPPI Channel 3 State Block
1C0h	TCPPIDMASTATEW0	Transmit CPPI DMA State Word 0
1C4h	TCPPIDMASTATEW1	Transmit CPPI DMA State Word 1
1C8h	TCPPIDMASTATEW2	Transmit CPPI DMA State Word 2
1CCh	TCPPIDMASTATEW3	Transmit CPPI DMA State Word 3
1D0h	TCPPIDMASTATEW4	Transmit CPPI DMA State Word 4
1D4h	TCPPIDMASTATEW5	Transmit CPPI DMA State Word 5
1DCh	TCPPICOMPPTR	Transmit CPPI Completion Pointer
1E0h	RCPPIDMASTATEW0	Receive CPPI DMA State Word 0
1E4h	RCPPIDMASTATEW1	Receive CPPI DMA State Word 1
1E8h	RCPPIDMASTATEW2	Receive CPPI DMA State Word 2
1ECh	RCPPIDMASTATEW3	Receive CPPI DMA State Word 3
1F0h	RCPPIDMASTATEW4	Receive CPPI DMA State Word 4
1F4h	RCPPIDMASTATEW5	Receive CPPI DMA State Word 5
1F8h	RCPPIDMASTATEW6	Receive CPPI DMA State Word 6
1FCh	RCPPICOMPPTR	Receive CPPI Completion Pointer
Common USB Registers
400h	FADDR	Function Address Register
401h	POWER	Power Management Register
402h	INTRTX	Interrupt Register for Endpoint 0 plus Transmit Endpoints 1 to 4
404h	INTRRX	Interrupt Register for Receive Endpoints 1 to 4
406h	INTRTXE	Interrupt enable register for INTRTX
408h	INTRRXE	Interrupt Enable Register for INTRRX
40Ah	INTRUSB	Interrupt Register for Common USB Interrupts
40Bh	INTRUSBE	Interrupt Enable Register for INTRUSB
40Ch	FRAME	Frame Number Register
40Eh	INDEX	Index Register for Selecting the Endpoint Status and Control Registers
40Fh	TESTMODE	Register to Enable the USB 2.0 Test Modes
Indexed Registers These registers operate on the endpoint selected by the INDEX register
410h	TXMAXP	Maximum Packet Size for Peripheral/Host Transmit Endpoint. (Index register set to select Endpoints 1-4)
412h	PERI_CSR0	Control Status Register for Endpoint 0 in Peripheral Mode. (Index register set to select Endpoint 0)
	HOST_CSR0	Control Status Register for Endpoint 0 in Host Mode. (Index register set to select Endpoint 0)
	PERI_TXCSR	Control Status Register for Peripheral Transmit Endpoint. (Index register set to select Endpoints 1-4)
	HOST_TXCSR	Control Status Register for Host Transmit Endpoint. (Index register set to select Endpoints 1-4)
414h	RXMAXP	Maximum Packet Size for Peripheral/Host Receive Endpoint. (Index register set to select Endpoints 1-4)
416h	PERI_RXCSR	Control Status Register for Peripheral Receive Endpoint. (Index register set to select Endpoints 1-4)
416h	HOST_RXCSR	Control Status Register for Host Receive Endpoint. (Index register set to select Endpoints 1-4)
418h	COUNT0	Number of Received Bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0)
418h	RXCOUNT	Number of Bytes in Host Receive Endpoint FIFO. (Index register set to select Endpoints 1- 4)
41Ah	HOST_TYPE0	Defines the speed of Endpoint 0
41Ah	HOST_TXTYPE	Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint. (Index register set to select Endpoints 1-4)
41Bh	HOST_NAKLIMIT0	Sets the NAK response timeout on Endpoint 0. (Index register set to select Endpoint 0)
41Bh	HOST_TXINTERVAL	Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint. (Index register set to select Endpoints 1-4)
41Ch	HOST_RXTYPE	Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint. (Index register set to select Endpoints 1-4)
41Dh	HOST_RXINTERVAL	Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint. (Index register set to select Endpoints 1-4)
41Fh	CONFIGDATA	Returns details of core configuration. (Index register set to select Endpoint 0)
FIFOn
420h	FIFO0	Transmit and Receive FIFO Register for Endpoint 0
424h	FIFO1	Transmit and Receive FIFO Register for Endpoint 1
428h	FIFO2	Transmit and Receive FIFO Register for Endpoint 2
42Ch	FIFO3	Transmit and Receive FIFO Register for Endpoint 3
430h	FIFO4	Transmit and Receive FIFO Register for Endpoint 4
OTG Device Control
460h	DEVCTL	OTG Device Control Register
Dynamic FIFO Control
462h	TXFIFOSZ	Transmit Endpoint FIFO Size (Index register set to select Endpoints 1-4)
463h	RXFIFOSZ	Receive Endpoint FIFO Size (Index register set to select Endpoints 1-4)
464h	TXFIFOADDR	Transmit Endpoint FIFO Address (Index register set to select Endpoints 1-4)
466h	RXFIFOADDR	Receive Endpoint FIFO Address (Index register set to select Endpoints 1-4)
Target Endpoint 0 Control Registers, Valid Only in Host Mode
480h	TXFUNCADDR	Address of the target function that has to be accessed through the associated Transmit Endpoint.
482h	TXHUBADDR	Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
483h	TXHUBPORT	Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
484h	RXFUNCADDR	Address of the target function that has to be accessed through the associated Receive Endpoint.
486h	RXHUBADDR	Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
487h	RXHUBPORT	Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Target Endpoint 1 Control Registers, Valid Only in Host Mode
488h	TXFUNCADDR	Address of the target function that has to be accessed through the associated Transmit Endpoint.
48Ah	TXHUBADDR	Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
48Bh	TXHUBPORT	Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
48Ch	RXFUNCADDR	Address of the target function that has to be accessed through the associated Receive Endpoint.
48Eh	RXHUBADDR	Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
48Fh	RXHUBPORT	Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Target Endpoint 2 Control Registers, Valid Only in Host Mode
490h	TXFUNCADDR	Address of the target function that has to be accessed through the associated Transmit Endpoint.
492h	TXHUBADDR	Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
493h	TXHUBPORT	Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
494h	RXFUNCADDR	Address of the target function that has to be accessed through the associated Receive Endpoint.
496h	RXHUBADDR	Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
497h	RXHUBPORT	Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Target Endpoint 3 Control Registers, Valid Only in Host Mode
498h	TXFUNCADDR	Address of the target function that has to be accessed through the associated Transmit Endpoint.
49Ah	TXHUBADDR	Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
49Bh	TXHUBPORT	Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
49Ch	RXFUNCADDR	Address of the target function that has to be accessed through the associated Receive Endpoint.
49Eh	RXHUBADDR	Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
49Fh	RXHUBPORT	Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Target Endpoint 4 Control Registers, Valid Only in Host Mode
4A0h	TXFUNCADDR	Address of the target function that has to be accessed through the associated Transmit Endpoint.
4A2h	TXHUBADDR	Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
4A3h	TXHUBPORT	Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
4A4h	RXFUNCADDR	Address of the target function that has to be accessed through the associated Receive Endpoint.
4A6h	RXHUBADDR	Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
4A7h	RXHUBPORT	Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Control and Status Register for Endpoint 0
502h	PERI_CSR0	Control Status Register for Endpoint 0 in Peripheral Mode
502h	HOST_CSR0	Control Status Register for Endpoint 0 in Host Mode
508h	COUNT0	Number of Received Bytes in Endpoint 0 FIFO
50Ah	HOST_TYPE0	Defines the Speed of Endpoint 0
50Bh	HOST_NAKLIMIT0	Sets the NAK Response Timeout on Endpoint 0
50Fh	CONFIGDATA	Returns details of core configuration.
Control and Status Register for Endpoint 1
510h	TXMAXP	Maximum Packet Size for Peripheral/Host Transmit Endpoint
512h	PERI_TXCSR	Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
512h	HOST_TXCSR	Control Status Register for Host Transmit Endpoint (host mode)
514h	RXMAXP	Maximum Packet Size for Peripheral/Host Receive Endpoint
516h	PERI_RXCSR	Control Status Register for Peripheral Receive Endpoint (peripheral mode)
516h	HOST_RXCSR	Control Status Register for Host Receive Endpoint (host mode)
518h	RXCOUNT	Number of Bytes in Host Receive endpoint FIFO
51Ah	HOST_TXTYPE	Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint.
51Bh	HOST_TXINTERVAL	Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint.
51Ch	HOST_RXTYPE	Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint.
51Dh	HOST_RXINTERVAL	Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint.
Control and Status Register for Endpoint 2
520h	TXMAXP	Maximum Packet Size for Peripheral/Host Transmit Endpoint
522h	PERI_TXCSR	Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
522h	HOST_TXCSR	Control Status Register for Host Transmit Endpoint (host mode)
524h	RXMAXP	Maximum Packet Size for Peripheral/Host Receive Endpoint
526h	PERI_RXCSR	Control Status Register for Peripheral Receive Endpoint (peripheral mode)
526h	HOST_RXCSR	Control Status Register for Host Receive Endpoint (host mode)
528h	RXCOUNT	Number of Bytes in Host Receive endpoint FIFO
52Ah	HOST_TXTYPE	Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint.
52Bh	HOST_TXINTERVAL	Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint.
52Ch	HOST_RXTYPE	Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint.
52Dh	HOST_RXINTERVAL	Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint.
Control and Status Register for Endpoint 3
530h	TXMAXP	Maximum Packet Size for Peripheral/Host Transmit Endpoint
532h	PERI_TXCSR	Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
532h	HOST_TXCSR	Control Status Register for Host Transmit Endpoint (host mode)
534h	RXMAXP	Maximum Packet Size for Peripheral/Host Receive Endpoint
536h	PERI_RXCSR	Control Status Register for Peripheral Receive Endpoint (peripheral mode)
536h	HOST_RXCSR	Control Status Register for Host Receive Endpoint (host mode)
538h	RXCOUNT	Number of Bytes in Host Receive endpoint FIFO
53Ah	HOST_TXTYPE	Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint.
53Bh	HOST_TXINTERVAL	Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint.
53Ch	HOST_RXTYPE	Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint.
53Dh	HOST_RXINTERVAL	Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint.
Control and Status Register for Endpoint 4
540h	TXMAXP	Maximum Packet Size for Peripheral/Host Transmit Endpoint
542h	PERI_TXCSR	Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
542h	HOST_TXCSR	Control Status Register for Host Transmit Endpoint (host mode)
544h	RXMAXP	Maximum Packet Size for Peripheral/Host Receive Endpoint
546h	PERI_RXCSR	Control Status Register for Peripheral Receive Endpoint (peripheral mode)
546h	HOST_RXCSR	Control Status Register for Host Receive Endpoint (host mode)
548h	RXCOUNT	Number of Bytes in Host Receive endpoint FIFO
54Ah	HOST_TXTYPE	Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint.
54Bh	HOST_TXINTERVAL	Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint.
54Ch	HOST_RXTYPE	Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint.
54Dh	HOST_RXINTERVAL	Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint.

7.13.2 USB2.0 Electrical Data/Timing

Table 7-57 Switching Characteristics Over Recommended Operating Conditions for USB2.0 (see Figure 7-41)

NO.	PARAMETER		DEVICE						UNIT
			LOW SPEED 1.5 Mbps		FULL SPEED 12 Mbps		HIGH SPEED⁽⁴⁾ 480 Mbps
			MIN	MAX	MIN	MAX	MIN	MAX
1	t_r(D)	Rise time, USB_DP and USB_DM signals⁽¹⁾	75	300	4	20	0.5	20	ns
2	t_f(D)	Fall time, USB_DP and USB_DM signals⁽¹⁾	75	300	4	20	0.5	20	ns
3	t_frfm	Rise/Fall time, matching⁽²⁾	80	125	90	111.11	–	–	%
4	V_CRS	Output signal cross-over voltage⁽¹⁾	1.3	2	1.3	2	–	–	V
5	t_jr(source)NT	Source (Host) Driver jitter, next transition		2		2			ns
	t_jr(FUNC)NT	Function Driver jitter, next transition		25		2			ns
6	t_jr(source)PT	Source (Host) Driver jitter, paired transition⁽³⁾		1		1			ns
	t_jr(FUNC)PT	Function Driver jitter, paired transition		10		1			ns
7	t_w(EOPT)	Pulse duration, EOP transmitter	1250	1500	160	175	–	–	ns
8	t_w(EOPR)	Pulse duration, EOP receiver	670		82		–		ns
9	t_(DRATE)	Data Rate		1.5		12		480	Mbps
10	Z_DRV	Driver Output Resistance	–	–	28	49.5	40.5	49.5	Ω

(1) Low Speed: C_L = 200 pF, Full Speed: C_L = 50 pF, High Speed: C_L = 50 pF

(2) t_frfm = (t_r/t_f) x 100. [Excluding the first transaction from the Idle state.]

(3) t_jr = t_px(1) - t_px(0)

(4) For more detailed specification information, see the Universal Serial Bus Specification Revision 2.0, Chapter 7.

Figure 7-41 USB2.0 Integrated Transceiver Interface Timing

7.14 Universal Asynchronous Receiver/Transmitter (UART)

The UART module performs serial-to-parallel conversion on data received from a peripheral device or modem, and parallel-to-serial conversion on data received from the CPU. Each UART also includes a programmable baud rate generator capable of dividing the module's reference clock by divisors from 1 to 65,535 to produce a 16 x clock driving the internal logic. The UART modules support the following features:

Frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates
16-byte storage space for both the transmitter and receiver FIFOs
Unique interrupts, one for each UART
Unique EDMA events, both received and transmitted data for each UART
1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA
Programmable auto-rts and auto-cts for autoflow control (supported on UART1)
Programmable serial data formats
- 5, 6, 7, or 8-bit characters
- Even, odd, or no parity bit generation and detection
- 1, 1.5, or 2 stop bit generation
False start bit detection
Line break generation and detection
Internal diagnostic capabilities
- Loopback controls for communications link fault isolation
- Break, parity, overrun, and framing error simulation
Modem control functions: CTS, RTS (supported on UART1)

7.14.1 UART Peripheral Register Description

Table 7-58 lists the UART registers, their corresponding acronyms, and the device memory locations (offsets).

Table 7-58 UART Registers

OFFSET	ACRONYM	REGISTER DESCRIPTION
0h	RBR	Receiver Buffer Register (read only)
0h	THR	Transmitter Holding Register (write only)
4h	IER	Interrupt Enable Register
8h	IIR	Interrupt Identification Register (read only)
8h	FCR	FIFO Control Register (write only)
Ch	LCR	Line Control Register
10h	MCR	Modem Control Register
14h	LSR	Line Status Register
20h	DLL	Divisor LSB Latch
24h	DLH	Divisor MSB Latch
28h	PID	Peripheral Identification Register
30h	PWREMU_MGMT	Power and Emulation Management Register
34h	MDR	Mode Definition Register

7.14.2 UART Electrical Data/Timing

Table 7-59 Timing Requirements for UARTx Receive (see Figure 7-42)⁽¹⁾

NO.			DEVICE		UNIT
NO.			MIN	MAX	UNIT
4	t_w(URXDB)	Pulse duration, receive data bit (RXDn)	.96U	1.05U	ns
5	t_w(URXSB)	Pulse duration, receive start bit	.96U	1.05U	ns

(1) U = UART baud time = 1/programmed baud rate.

Table 7-60 Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit
(see Figure 7-42)⁽¹⁾

NO.	PARAMETER		DEVICE		UNIT
NO.	PARAMETER		MIN	MAX	UNIT
1	f_(baud)	UART0 Maximum programmable baud rate		5	MHz
1	f_(baud)	UART1 Maximum programmable baud rate		5	MHz
2	t_w(UTXDB)	Pulse duration, transmit data bit (TXDn)	U - 2	U + 2	ns
3	t_w(UTXSB)	Pulse duration, transmit start bit	U - 2	U + 2	ns

(1) U = UART baud time = 1/programmed baud rate.

Figure 7-42 UART Transmit/Receive Timing

7.15 Serial Port Interface (SPI)

The SPI module provides a programmable length shift register which allows serial communication with other SPI devices through a 3 or 4 wire interface (Clock, Data In, Data Out, and Chip-select). The SPI supports the following features:

Master and Slave mode operation is supported on all SPI ports (master mode means that the device provides the serial clock)
2 chip selects for interfacing to multiple slave SPI devices.
3 or 4 wire interface (Clock, Data In, Data Out, and Enable)
Unique interrupt for each SPI port (except SPI4)
Separate EDMA events for SPI Receive and Transmit for each SPI port (except SPI4)
16-bit shift register
Receive buffer register
Programmable character length (2 to 16 bits)
Programmable SPI clock frequency range
8-bit clock prescaler
Programmable clock phase (delay or no delay)
Programmable clock polarity

Note: SPI4 slave mode does not support Chip-select input, only supports 3-wire interface.

The SPI modules do not support the following features:

GPIO mode. GPIO functionality is supported by the GIO modules for those SPI pins that are multiplexed with GPIO signals.

7.15.1 SPI Peripheral Register Description

Table 7-61 lists the SPI registers, their corresponding acronyms, and the device memory locations (offsets). These offsets apply to all device SPI modules.

Table 7-61 SPI Registers

OFFSET	ACRONYM	REGISTER DESCRIPTION
00h	SPIGCR0	SPI global control register 0
04h	SPIGCR1	SPI global control register 1
08h	SPIINT	SPI interrupt register
0Ch	SPILVL	SPI interrupt level register
10h	SPIFLG	SPI flag register
14h	SPIPC0	SPI pin control register
18h	-	Reserved
1Ch	SPIPC2	SPI pin control register 2
20h - 38h	-	Reserved
3Ch	SPIDAT1	SPI shift register
40h	SPIBUF	SPI buffer register
44h	SPIEMU	SPI emulation register
48h	SPIDELAY	SPI delay register
4Ch	SPIDEF	SPI default chip select register
50h-5Ch	SPIFMT0	SPI data format register 0
60h	INTVECT0	SPI interrupt vector register 0
64h	INTVECT1	SPI interrupt vector register 1

7.15.2 SPI Electrical Data/Timing

7.15.2.1 Master Mode — General

Table 7-62 General Switching Characteristics in Master Mode⁽¹⁾

NO.	PARAMETER		MIN	MAX	UNIT
1	t_c(CLK)	Cycle time, SPI_SCLK	greater of 2P or 25	256P	ns
2	t_w(CLKH)	Pulse width, SPI_SCLK high	.5(t_c(CLK)) - 1.25		ns
3	t_w(CLKL)	Pulse width, SPI_SCLK low	.5(t_c(CLK)) - 1.25		ns
4	t_{osu(SIMO-CLK)}	Output setup time, SPI_SIMO valid (1st bit) before initial SPI_SCLK rising edge, 3- and4-pin mode, polarity = 0, phase = 0	6.5		ns
		Output setup time, SPI_SIMO valid (1st bit) before initial SPI_SCLK rising edge, 3- and4-pin mode, polarity = 0, phase = 1	.5t_c(CLK) + 6.5
		Output setup time, SPI_SIMO valid (1st bit) before initial SPI_SCLK falling edge, 3- and4-pin mode, polarity = 1, phase = 0	6.5
		Output setup time, SPI_SIMO valid (1st bit) before initial SPI_SCLK falling edge, 3- and4-pin mode, polarity = 1, phase = 1	.5t_c(CLK) + 6.5
5	t_d(CLK-SIMO)	Delay time, SPI_SCLK transmit rising edge to SPI_SIMO output valid (subsequent bit driven), 3- and4-pin mode, polarity = 0, phase = 0	-3	6	ns
		Delay time, SPI_SCLK transmit falling edge to SPI_SIMO output valid (subsequent bit driven), 3- and4-pin mode, polarity = 0, phase = 1	-3	6
		Delay time, SPI_SCLK transmit falling edge to SPI_SIMO output valid (subsequent bit driven), 3- and4-pin mode, polarity = 1, phase = 0	-3	6
		Delay time, SPI_SCLK transmit rising edge to SPI_SIMO output valid (subsequent bit driven), 3- and4-pin mode, polarity = 1, phase = 1	-3	6
6	t_oh(CLK-SIMO)	Output hold time, SPI_SIMO valid (except final bit) after receive falling edge of SPI_SCLK, 3- and4-pin mode, polarity = 0, phase = 0	9.5		ns
		Output hold time, SPI_SIMO valid (except final bit) after receive rising edge of SPI_SCLK, 3- and4-pin mode, polarity = 0, phase = 1	9.5
		Output hold time, SPI_SIMO valid (except final bit) after receive rising edge of SPI_SCLK, 3- and4-pin mode, polarity = 1, phase = 0	9.5
		Output hold time, SPI_SIMO valid (except final bit) after receive falling edge of SPI_SCLK, 3- and4-pin mode, polarity = 1, phase = 1	9.5

(1) T = period of SPI_SCLK; For SPI0, SPI1, SPI2, and SPI3, P = period of SPI core clock (PLL1SYSCLK4). For SPI4, P = period of SPI core clock (OSCIN).

Table 7-63 General Input Timing Requirements in Master Mode

NO.			MIN	UNIT
7	t_su(SOMI-CLK)	Setup time, SPI_SOMI valid before receive falling edge of SPI_SCLK, 3- and4-pin mode, polarity = 0, phase = 0	4	ns
		Setup time, SPI_SOMI valid before receive rising edge of SPI_SCLK, 3- and4-pin mode, polarity = 0, phase = 1	4
		Setup time, SPI_SOMI valid before receive rising edge of SPI_SCLK, 3- and4-pin mode, polarity = 1, phase = 0	4
		Setup time, SPI_SOMI valid before receive falling edge of SPI_SCLK, 3- and4-pin mode, polarity = 1, phase = 1	4
8	t_h(CLK-SOMI)	Hold time, SPI_SOMI valid after receive falling edge of SPI_SCLK, 3- and4-pin mode, polarity = 0, phase = 0	4	ns
		Hold time, SPI_SOMI valid after receive rising edge of SPI_SCLK, 3- and4-pin mode, polarity = 0, phase = 1	4
		Hold time, SPI_SOMI valid after receive rising edge of SPI_SCLK, 3- and4-pin mode, polarity = 1, phase = 0	4
		Hold time, SPI_SOMI valid after receive falling edge of SPI_SCLK, 3- and4-pin mode, polarity = 1, phase = 1	4

7.15.2.2 Slave Mode — General

Table 7-64 General Switching Characteristics in Slave Mode (For 3- and4-Pin Modes)⁽¹⁾

NO.	PARAMETER		MIN	MAX	UNIT
13	t_d(CLK-SOMI)	Delay time, transmit rising edge of SPI_SCLK to SPI_SOMI output valid, 3- and4-pin mode, polarity = 0, phase = 0	2	16.5	ns
		Delay time, transmit falling edge of SPI_SCLK to SPI_SOMI output valid, 3- and4-pin mode, polarity = 0, phase = 1	2	16.5
		Delay time, transmit falling edge of SPI_SCLK to SPI_SOMI output valid, 3- and4-pin mode, polarity = 1, phase = 0	2	16.5
		Delay time, transmit rising edge of SPI_SCLK to SPI_SOMI output valid, 3- and4-pin mode, polarity = 1, phase = 1	2	16.5
14	t_oh(CLK-SOMI)	Output hold time, SPI_SOMI valid (except final bit) after receive falling edge of SPI_SCLK, 3- and4-pin mode, polarity = 0, phase = 0	4		ns
		Output hold time, SPI_SOMI valid (except final bit) after receive rising edge of SPI_SCLK, 3- and4-pin mode, polarity = 0, phase = 1	4
		Output hold time, SPI_SOMI valid (except final bit) after receive rising edge of SPI_SCLK, 3- and4-pin mode, polarity = 1, phase = 0	4
		Output hold time, SPI_SOMI valid (except final bit) after receive falling edge of SPI_SCLK, 3- and4-pin mode, polarity = 1, phase = 1	4

(1) T = period of SPI_SCLK

Table 7-65 General Input Timing Requirements in Slave Mode⁽¹⁾

NO.			MIN	MAX	UNIT
9	t_c(CLK)	Cycle time, SPI_SCLK	greater of 2P or 25	256P	ns
10	t_w(CLKH)	Pulse width, SPI_SCLK high	.5(t_c(CLK)) - 1.25		ns
11	t_w(CLKL)	Pulse width, SPI_SCLK low	.5(t_c(CLK)) - 1.25		ns
15	t_su(SIMO-CLK)	Setup time, SPI_SIMO data valid before receive falling edge of SPI_SCLK, 3- and4-pin mode, polarity = 0, phase = 0	4		ns
		Setup time, SPI_SIMO data valid before receive rising edge of SPI_SCLK, 3- and4-pin mode, polarity = 0, phase = 1	4
		Setup time, SPI_SIMO data valid before receive rising edge of SPI_SCLK, 3- and4-pin mode, polarity = 1, phase = 0	4
		Setup time, SPI_SIMO data valid before receive falling edge of SPI_SCLK, 3- and4-pin mode, polarity = 1, phase = 1	4
16	t_h(CLK-SIMO)	Hold time, SPI_SIMO data valid after receive falling edge of SPI_SCLK, 3- and4-pin mode, polarity = 0, phase = 0	4		ns
		Hold time, SPI_SIMO data valid after receive rising edge of SPI_SCLK, 3- and4-pin mode, polarity = 0, phase = 1	4
		Hold time, SPI_SIMO data valid after receive rising edge of SPI_SCLK, 3- and4-pin mode, polarity = 1, phase = 0	4
		Hold time, SPI_SIMO data valid after receive falling edge of SPI_SCLK, 3- and4-pin mode, polarity = 1, phase = 1	4

(1) T = period of SPI_SCLK; For SPI0, SPI1, SPI2, and SPI3, P = period of SPI core clock (PLL1SYSCLK4). For SPI4, P = period of SPI core clock (OSCIN).

7.15.2.3 Master Mode — Additional

Table 7-66 Additional Output Switching Characteristics of 4-Pin Chip-Select Option in Master Mode

NO.	PARAMETER		MIN	UNIT
19	t_osu(CS-CLK) ⁽¹⁾	Output setup time, SPI_SCS[n] active before first SPI_SCLK rising edge, polarity = 0, phase = 0, SPIDELAY.C2TDELAY = 0	(C2TDELAY+2)*P+6.5	ns
		Output setup time, SPI_SCS[n] active before first SPI_SCLK rising edge, polarity = 0, phase = 1, SPIDELAY.C2TDELAY = 0	(C2TDELAY+2)*P + .5tc + 6.5
		Output setup time, SPI_SCS[n] active before first SPI_SCLK falling edge, polarity = 1, phase = 0, SPIDELAY.C2TDELAY = 0	(C2TDELAY+2)*P + 6.5
		Output setup time, SPI_SCS[n] active before first SPI_SCLK falling edge, polarity = 1, phase = 1, SPIDELAY.C2TDELAY = 0	(C2TDELAY+2)*P + .5tc + 6.5
20	t_d(CLK-CS)	Delay time, final SPI_SCLK falling edge to master deasserting SPI_SCS[n], polarity = 0, phase = 0, SPIDELAY.T2CDELAY = 0, SPIDAT1.CSHOLD not enabled	(T2CDELAY+1)*P - 3	ns
		Delay time, final SPI_SCLK falling edge to master deasserting SPI_SCS[n], polarity = 0, phase = 1, SPIDELAY.T2CDELAY = 0, SPIDAT1.CSHOLD not enabled	(T2CDELAY+1)*P - 3
		Delay time, final SPI_SCLK rising edge to master deasserting SPI_SCS[n], polarity = 1, phase = 0, SPIDELAY.T2CDELAY = 0, SPIDAT1.CSHOLD not enabled	(T2CDELAY+1)*P - 3
		Delay time, final SPI_SCLK rising edge to master deasserting SPI_SCS[n], polarity = 1, phase = 1, SPIDELAY.T2CDELAY = 0, SPIDAT1.CSHOLD not enabled	(T2CDELAY+1)*P - 3

(1) The Master SPI is ready with new data before SPI_SCS[n] assertion.

7.15.2.4 Slave Mode — Additional

Table 7-67 Additional Output Switching Characteristics of 4-Pin Chip-Select Option in Slave Mode⁽¹⁾

NO.	PARAMETER		MIN	MAX	UNIT
27	t_d(CSL-SOMI)	Delay time, master asserting SPI_SCS[n] to slave driving SPI_SOMI data valid		2P + 16.5	ns
28	t_{dis(CSH-SOMI)}	Disable time, master deasserting SPI_SCS[n] to slave driving SPI_SOMI high impedance		2P + 16.5	ns

(1) T = period of SPI_SCLK; For SPI0, SPI1, SPI2, and SPI3, P = period of SPI core clock (PLL1SYSCLK4). For SPI4, P = period of SPI core clock (OSCIN).

Table 7-68 Additional Input Timing Requirements of 4-Pin Chip-Select Option in Slave Mode⁽¹⁾

NO.			MIN	UNIT
25	t_su(CSL-CLK)	Setup time, SPI_SCS[n] asserted at slave to first SPI_SCLK edge (rising or falling) at slave	2P + 25	ns
26	t_d(CLK-CSH)	Delay time, final falling edge SPI_SCLK to SPI_SCS[n] deasserted, polarity = 0, phase = 0	.5(t_c(CLK)) + 2P - 4	ns
		Delay time, final falling edge SPI_SCLK to SPI_SCS[n] deasserted, polarity = 0, phase = 1	2P - 4
		Delay time, final rising edge SPI_SCLK to SPI_SCS[n] deasserted, polarity = 1, phase = 0	.5(t_c(CLK)) + 2P - 4
		Delay time, final rising edge SPI_SCLK to SPI_SCS[n] deasserted, polarity = 1, phase = 1	2P - 4

(1) T = period of SPI_SCLK; For SPI0, SPI1, SPI2, and SPI3, P = period of SPI core clock (PLL1SYSCLK4). For SPI4, P = period of SPI core clock (OSCIN).

Figure 7-43 SPI Timings—Master Mode

A. The first bit of transmit data becomes valid on the SPI_SOMI pin when software writes to the SPIDAT1 register. For more details, see the TMS320DM36x DMSoC Serial Peripheral Interface User's Guide (SPRUFH1).

Figure 7-44 SPI Timings—Slave Mode

Figure 7-45 SPI Timings—Master Mode (4-Pin)

Figure 7-46 SPI Timings—Slave Mode (4-Pin)

7.16 Inter-Integrated Circuit (I2C)

The inter-integrated circuit (I2C) module provides an interface between the DM369 and other devices compliant with Philips Semiconductors Inter-IC bus (I²C-bus) specification version 2.1 and connected by way of an I²C-bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the device through the I2C module.

The I2C port supports:

Compatible with Philips I²C Specification Revision 2.1 (January 2000)
Fast Mode up to 400 Kbps (no fail-safe I/O buffers)
Noise Filter to Remove Noise 50 ns or less
Seven- and Ten-Bit Device Addressing Modes
Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
Events: DMA, Interrupt, or Polling

For more detailed information on the I2C peripheral, see the device TMS320DM36x Digital Media System-on-Chip (DMSoC) Inter-Integrated Circuit (I2C) Peripheral User's Guide.

7.16.1 I2C Peripheral Register Description

Table 7-69 lists the I2C registers, their corresponding acronyms, and the device memory locations (offsets).

Table 7-69 Inter-Integrated Circuit (I2C) Registers

Offset	Acronym	Register Description
0h	ICOAR	I2C Own Address Register
4h	ICIMR	I2C Interrupt Mask Register
8h	ICSTR	I2C Interrupt Status Register
Ch	ICCLKL	I2C Clock Low-Time Divider Register
10h	ICCLKH	I2C Clock High-Time Divider Register
14h	ICCNT	I2C Data Count Register
18h	ICDRR	I2C Data Receive Register
1Ch	ICSAR	I2C Slave Address Register
20h	ICDXR	I2C Data Transmit Register
24h	ICMDR	I2C Mode Register
28h	ICIVR	I2C Interrupt Vector Register
2Ch	ICEMDR	I2C Extended Mode Register
30h	ICPSC	I2C Prescaler Register
34h	REVID1	I2C Revision ID Register 1
38h	REVID2	I2C Revision ID Register 2
48h	ICPFUNC	I2C Pin Function Register
4ch	ICPDIR	I2C Pin Direction Register
50h	ICPDIN	I2C Pin Data In Register
54h	ICPDOUT	I2C Pin Data Out Register
58h	ICPDSET	I2C Pin Data Set Register
5ch	ICPDCLR	I2C Pin Data Clear register

7.16.2 I2C Electrical Data/Timing

7.16.2.1 Inter-Integrated Circuits (I2C) Timing

Table 7-70 Timing Requirements for I2C Timings⁽¹⁾ (see Figure 7-47)

NO.			DEVICE				UNIT
			STANDARD MODE		FAST MODE
			MIN	MAX	MIN	MAX
1	t_c(SCL)	Cycle time, SCL	10		2.5		μs
2	t_{su(SCLH-SDAL)}	Setup time, SCL high before SDA low (for a repeated START condition)	4.7		0.6		μs
3	t_h(SCLL-SDAL)	Hold time, SCL low after SDA low (for a START and a repeated START condition)	4		0.6		μs
4	t_w(SCLL)	Pulse duration, SCL low	4.7		1.3		μs
5	t_w(SCLH)	Pulse duration, SCL high	4		0.6		μs
6	t_{su(SDAV-SCLH)}	Setup time, SDA valid before SCL high	250		100		ns
7	t_h(SDA-SCLL)	Hold time, SDA valid after SCL low (For I²C bus™ devices)	0	3.45	0	0.9	μs
8	t_w(SDAH)	Pulse duration, SDA high between STOP and START conditions	4.7		1.3		μs
9	t_r(SDA)	Rise time, SDA		1000	20 + 0.1C_b ⁽¹⁾	300	ns
10	t_r(SCL)	Rise time, SCL		1000	20 + 0.1C_b ⁽¹⁾	300	ns
11	t_f(SDA)	Fall time, SDA		300	20 + 0.1C_b ⁽¹⁾	300	ns
12	t_f(SCL)	Fall time, SCL		300	20 + 0.1C_b ⁽¹⁾	300	ns
13	t_{su(SCLH-SDAH)}	Setup time, SCL high before SDA high (for STOP condition)	4		0.6		μs
14	t_w(SP)	Pulse duration, spike (must be suppressed)				50	ns
15	C_b ⁽²⁾	Capacitive load for each bus line		400		400	pF

(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.

(2) C_b = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

Figure 7-47 I2C Receive Timings

Table 7-71 Switching Characteristics for I2C Timings⁽¹⁾ (see Figure 7-48)

NO.	PARAMETER		DEVICE				UNIT
			STANDARD MODE		FAST MODE
			MIN	MAX	MIN	MAX
16	t_c(SCL)	Cycle time, SCL	10		2.5		μs
17	t_d(SCLH-SDAL)	Delay time, SCL high to SDA low (for a repeated START condition)	4.7		0.6		μs
18	t_d(SDAL-SCLL)	Delay time, SDA low to SCL low (for a START and a repeated START condition)	4		0.6		μs
19	t_w(SCLL)	Pulse duration, SCL low	4.7		1.3		μs
20	t_w(SCLH)	Pulse duration, SCL high	4		0.6		μs
21	t_d(SDAV-SCLH)	Delay time, SDA valid to SCL high	250		100		ns
22	t_v(SCLL-SDAV)	Valid time, SDA valid after SCL low (For I2C devices)	0		0	0.9	μs
23	t_w(SDAH)	Pulse duration, SDA high between STOP and START conditions	4.7		1.3		μs
28	t_d(SCLH-SDAH)	Delay time, SCL high to SDA high (for STOP condition)	4		0.6		μs
29	C_p	Capacitance for each I2C pin		10		10	pF

(1) C_b = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

CAUTION

The I²C pins use a standard ±4-mA LVCMOS buffer, not the slow I/OP buffer defined in the I²C specification. Series resistors may be necessary to reduce noise at the system level.

Figure 7-48 I2C Transmit Timings

7.17 Multichannel Buffered Serial Port (McBSP)

The primary use for the multichannel Buffered Serial Port (McBSP) is for audio interface purposes. The primary audio modes that are supported by the McBSP are the AC97 and IIS modes. In addition to the primary audio modes, the McBSP supports general serial port receive and transmit operation, but is not intended to be used as a high-speed interface. The McBSP supports the following features:

Full-duplex communication
Double-buffered data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
External shift clock generation or an internal programmable frequency shift clock
Double-buffered data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected analog-to-digital (A/D) and digital-to-analog (D/A) devices
Direct interface to AC97 compliant devices (the necessary multiphase frame synchronization capability is provided)
Direct interface to IIS compliant devices
Direct interface to SPI protocol in master mode only
A wide selection of data sizes, including 8, 12, 16, 20, 24, and 32 bits
μ-Law and A-Law companding
8-bit data transfers with the option of LSB or MSB first
Programmable polarity for both frame synchronization and data clocks
Highly programmable internal clock and frame generation
Direct interface to T1/E1 Framers
multichannel transmit and receive of up to 128 channels

For more detailed information on the McBSP peripheral, see the Multichannel Buffered Serial Port (McBSP) User's Guide (SPRUFI3).

7.17.1 McBSP Peripheral Register Description

Table 7-72 lists the McBSP registers, their corresponding acronyms, and the device memory locations (offsets).

Table 7-72 McBSP Registers

Offset	Acronym	Register Name
-	RBR⁽¹⁾	Receive buffer register
-	RSR⁽¹⁾	Receive shift register
-	XSR⁽¹⁾	Transmit shift register
00h	DRR⁽²⁾ ⁽³⁾	Data receive register
04h	DXR⁽³⁾	Data transmit register
08h	SPCR	Serial port control register
0Ch	RCR	Receive control register
10h	XCR	Transmit control register
14h	SRGR	Sample rate generator register
18h	MCR	Multichannel Control Register
1Ch	RCERE0	Enhanced Receive Channel Enable Register 0 Partition A/B
20h	XCERE0	Enhanced Transmit Channel Enable Register 0 Partition A/B
24h	PCR	Pin control register
28h	RCERE1	Enhanced Receive Channel Enable Register 1 Partition C/D
2Ch	XCERE1	Enhanced Transmit Channel Enable Register 1 Partition C/D
30h	RCERE2	Enhanced Receive Channel Enable Register 2 Partition E/F
34h	XCERE2	Enhanced Transmit Channel Enable Register 2 Partition E/F
38h	RCERE3	Enhanced Receive Channel Enable Register 3 Partition G/H
3Ch	XCERE3	Enhanced Transmit Channel Enable Register 3 Partition G/H

(1) The RBR, RSR, and XSR are not directly accessible via the CPUs or the EDMA controller.

(2) The CPUs and EDMA controller can only read this register; they cannot write to it.

(3) The DRR and DXR are accessible via the CPUs or the EDMA controller.

7.17.2 McBSP Electrical Data/Timing

7.17.2.1 multichannel Buffered Serial Port (McBSP) Timing

Table 7-73 Timing Requirements for McBSP⁽¹⁾ ⁽²⁾ (see Figure 7-49)

NO.				DEVICE		UNIT
NO.				MIN	MAX	UNIT
15⁽⁴⁾	t_c(CLKS)	Cycle time, CLKS	CLKS ext	38.5 or 2P		ns
16⁽³⁾	t_w(CLKS)	Pulse duration, CLKR/X high or CLKR/X low	CLKS ext	19.25 or P		ns
5	t_su(FRH-CKRL)	Setup time, external FSR high before CLKR low	CLKR int	21		ns
5	t_su(FRH-CKRL)	Setup time, external FSR high before CLKR low	CLKR ext	6		ns
6	t_h(CKRL-FRH)	Hold time, external FSR high after CLKR low	CLKR int	0		ns
6	t_h(CKRL-FRH)	Hold time, external FSR high after CLKR low	CLKR ext	6		ns
7	t_su(DRV-CKRL)	Setup time, DR valid before CLKR low	CLKR int	21		ns
7	t_su(DRV-CKRL)	Setup time, DR valid before CLKR low	CLKR ext	6		ns
8	t_h(CKRL-DRV)	Hold time, DR valid after CLKR low	CLKR int	0		ns
8	t_h(CKRL-DRV)	Hold time, DR valid after CLKR low	CLKR ext	6		ns
10	t_su(FXH-CKXL)	Setup time, external FSX high before CLKX low	CLKX int	21		ns
10	t_su(FXH-CKXL)	Setup time, external FSX high before CLKX low	CLKX ext	6		ns
11	t_h(CKXL-FXH)	Hold time, external FSX high after CLKX low	CLKX int	0		ns
11	t_h(CKXL-FXH)	Hold time, external FSX high after CLKX low	CLKX ext	10		ns

(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

(2) P = (1/SYSCLK4), where SYSCLK4 is an output clock of PLLC1 (see Section 4.3) .

(3) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.

(4) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.

Table 7-74 Switching Characteristics Over Recommended Operating Conditions for McBSP⁽¹⁾ ⁽²⁾ ⁽³⁾
(see Figure 7-49)

NO.	PARAMETER			DEVICE		UNIT
NO.	PARAMETER			MIN	MAX	UNIT
2⁽⁴⁾ ⁽⁵⁾	t_c(CKRX)	Cycle time, CLKR/X	CLKR/X int	38.5 or 2P		ns
2⁽⁴⁾ ⁽⁵⁾	t_c(CKRX)	Cycle time, CLKR/X	CLKR/X ext	38.5 or 2P		ns
17	t_d(CLKS-CLKRX)	Delay time, CLKS high to internal CLKR/X	CLKR/X int	1	24
3⁽⁶⁾	t_w(CKRX)	Pulse duration, CLKR/X high or CLKR/X low	CLKR/X int	19.25 - 1 or P - 1		ns
3⁽⁶⁾	t_w(CKRX)	Pulse duration, CLKR/X high or CLKR/X low	CLKR/X ext	19.25 or P		ns
4	t_d(CKRH-FRV)	Delay time, CLKR high to internal FSR valid	CLKR int	-4	8	ns
4	t_d(CKRH-FRV)	Delay time, CLKR high to internal FSR valid	CLKR ext	3	25	ns
9	t_d(CKXH-FXV)	Delay time, CLKX high to internal FSX valid	CLKX int	-4	8	ns
9	t_d(CKXH-FXV)	Delay time, CLKX high to internal FSX valid	CLKX ext	3	25	ns
12	tdis(CKXH-DXHZ)	Disable time, DX high impedance following last data bit from CLKX high	CLKX int		12	ns
12	tdis(CKXH-DXHZ)		CLKX ext		25	ns
13	t_d(CKXH-DXV)	Delay time, CLKX high to DX valid	CLKX int	-5 + D1⁽⁷⁾	12 + D2⁽⁷⁾	ns
13	t_d(CKXH-DXV)	Delay time, CLKX high to DX valid	CLKX ext	3 + D1⁽⁷⁾	25 + D2⁽⁷⁾	ns
14	t_d(FXH-DXV)	Delay time, FSX high to DX valid ONLY applies when in data delay 0 (XDATDLY = 00b) mode	FSX int	0 + D1⁽⁸⁾	14 + D2⁽⁸⁾	ns
14	t_d(FXH-DXV)		FSX ext	0 + D1⁽⁸⁾	25 + D2⁽⁸⁾	ns

(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

(2) Minimum delay times also represent minimum output hold times.

(3) P = (1/SYSCLK4), where SYSCLK4 is an output clock of PLLC1 (see Section 4.3) .

(4) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source.

(5) The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements. Use whichever value is greater.

(6) C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = SYSCLK3 period)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit.

(7) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
If DXENA = 0, then D1 = D2 = 0
If DXENA = 1, then D1 = 6P, D2 = 12P

(8) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
If DXENA = 0, then D1 = D2 = 0
If DXENA = 1, then D1 = 6P, D2 = 12P

Figure 7-49 McBSP Timing

Table 7-75 McBSP as SPI Timing Requirements

CLKSTP = 10b, CLKXP = 0 (see Figure 7-50)

NO.			MASTER		UNIT
NO.			MIN	MAX	UNIT
M30	t_su(DRV-CKXL)	Setup time, DR valid before CLKX low	16		ns
M31	t_h(CKXL-DRV)	Hold time, DR valid after CLKX low	0		ns

Table 7-76 McBSP as SPI Switching Characteristics⁽¹⁾ ⁽²⁾

CLKSTP = 10b, CLKXP = 0 (see Figure 7-50)

NO.	PARAMETER		MASTER		UNIT
NO.	PARAMETER		MIN	MAX	UNIT
M33	tc(CKX)	Cycle time, CLKX	38.5 or 2P		ns
M24	t_d(CKXL-FXH)	Delay time, CLKX low to FSX high⁽²⁾	CLKXP - 2	CLKXP + 4	ns
M25	t_d(FXL-CKXH)	Delay time, FSX low to CLKX high⁽³⁾	CLKXL - 2	CLKXL + 2	ns
M26	t_d(CKXH-DXV)	Delay time, CLKX high to DX valid	-2	6	ns
M27	t_{dis(CKXL-DXHZ)}	Disable time, DX high impedance following last data bit from CLKX low	CLKXL - 3	CLKXL + 8	ns

(1) P = (1/SYSCLK4), where SYSCLK4 is an output clock of PLLC1 (see Section 4.3) .

(2) T = CLKX period = (1 + CLKGDV) × 2P
L₁ = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) × 2P when CLKGDV is even.

(3) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

Figure 7-50 McBSP as SPI: CLKSTP = 10b, CLKXP = 0

Table 7-77 McBSP as SPI Timing Requirements

CLKSTP = 11b, CLKXP = 0

NO.			MASTER		UNIT
NO.			MIN	MAX	UNIT
M39	t_su(DRV-CKXH)	Setup time, DR valid before CLKX high	16		ns
M40	t_h(CKXH-DRV)	Hold time, DR valid after CLKX high	1		ns

Table 7-78 McBSP as SPI Switching Characteristics⁽¹⁾ ⁽²⁾

CLKSTP = 11b, CLKXP = 0 (see Figure 7-51)

NO.	PARAMETER		MASTER		UNIT
NO.	PARAMETER		MIN	MAX	UNIT
M42	tc(CKX)	Cycle time, CLKX	38.5 or 2P		ns
M34	t_d(CKXL-FXH)	Delay time, CLKX low to FSX high⁽³⁾	CLKXP - 2	CLKXP + 4	ns
M35	t_d(FXL-CKXH)	Delay time, FSX low to CLKX high⁽⁴⁾	CLKXP - 2	CLKXP + 2	ns
M36	t_d(CKXL-DXV)	Delay time, CLKX low to DX valid	-2	6	ns
M37	t_{dis(CKXL-DXHZ)}	Disable time, DX high impedance following last data bit from CLKX low	-3	8	ns
M38	t_d(FXL-DXV)	Delay time, FSX low to DX valid	CLKXH - 2	CLKXH + 10	ns

(1) P = (1/SYSCLK4), where SYSCLK4 is an output clock of PLLC1 (see Section 4.3).

(2) T = CLKX period = (1 + CLKGDV) × 2P
L₁ = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) × 2P when CLKGDV is even
H₁ = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) × 2P when CLKGDV is even

(3) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

(4) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

Figure 7-51 McBSP as SPI: CLKSTP = 11b, CLKXP = 0

Table 7-79 McBSP as SPI Timing Requirements

CLKSTP = 10b, CLKXP = 1 (see Figure 7-52)

NO.			MASTER		UNIT
NO.			MIN	MAX	UNIT
M49	t_su(DRV-CKXH)	Setup time, DR valid before CLKX high	16		ns
M50	t_h(CKXH-DRV)	Hold time, DR valid after CLKX high	0		ns

Table 7-80 McBSP as SPI Switching Characteristics⁽¹⁾ ⁽²⁾

CLKSTP = 10b, CLKXP = 1 (see Figure 7-52)

NO.	PARAMETER		MASTER		UNIT
NO.	PARAMETER		MIN	MAX	UNIT
M52	tc(CKX)	Cycle time, CLKX	38.5 or 2P		ns
M43	t_d(CKXH-FXH)	Delay time, CLKX high to FSX high⁽³⁾	CLKXP - 2	CLKXP + 4	ns
M44	t_d(FXL-CKXL)	Delay time, FSX low to CLKX low⁽⁴⁾	CLKXH - 2	CLKXH + 2	ns
M45	t_d(CKXL-DXV)	Delay time, CLKX low to DX valid	-2	6	ns
M46	t_{dis(CKXH-DXHZ)}	Disable time, DX high impedance following last data bit from CLKX high	CLKXH - 3	CLKXL + 8	ns

(1) P = (1/SYSCLK4), where SYSCLK4 is an output clock of PLLC1 (see Section 4.3).

(2) T = CLKX period = (1 + CLKGDV) × 2P
H₁ = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) × 2P when CLKGDV is even

(3) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

(4) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

Figure 7-52 McBSP as SPI: CLKSTP = 10b, CLKXP = 1

Table 7-81 McBSP as SPI Timing Requirements

CLKSTP = 11b, CLKXP = 1 (see Figure 7-53)

NO.			MASTER		UNIT
NO.			MIN	MAX	UNIT
M58	t_su(DRV-CKXL)	Setup time, DR valid before CLKX low	16		ns
M59	t_h(CKXL-DRV)	Hold time, DR valid after CLKX low	0		ns

Table 7-82 McBSP as SPI Switching Characteristics⁽¹⁾ ⁽²⁾

CLKSTP = 11b, CLKXP = 1 (see Figure 7-53)

NO.	PARAMETER		MASTER		UNIT
NO.	PARAMETER		MIN	MAX	UNIT
M62	tc(CKX)	Cycle time, CLKX	38.5 or 2P		ns
M53	t_d(CKXH-FXH)	Delay time, CLKX high to FSX high⁽³⁾	CLKXP - 2	CLKXP + 4	ns
M54	t_d(FXL-CKXL)	Delay time, FSX low to CLKX low⁽⁴⁾	CLKXP - 2	CLKXP + 2	ns
M55	t_d(CKXL-DXV)	Delay time, CLKX high to DX valid	-2	6	ns
M56	t_{dis(CKXH-DXHZ)}	Disable time, DX high impedance following last data bit from CLKX high	-3	8	ns
M57	t_d(FXL-DXV)	Delay time, FSX low to DX valid	CLKXL - 1	CLKXL + 10	ns

(1) P = (1/SYSCLK4), where SYSCLK4 is an output clock of PLLC1 (see Section 4.3).

Figure 7-53 McBSP as SPI: CLKSTP = 11b, CLKXP = 1

7.18 Timer

The device contains four software-programmable timers. Timer 0, Timer 1, Timer 3, and Timer 4 (general-purpose timers) can be programmed in 64-bit mode, dual 32-bit unchained mode, or dual 32-bit chained mode. Timer 3 supports additional features over the other timers: external clock/event input, period reload, output event tied to Real Time Out (RTO) module, external event capture, and timer counter register read reset. Timer 2 is used only as a watchdog timer. Timer 2 is tied to device reset.

64-bit count-up counter
Timer modes:
- 64-bit general-purpose timer mode (Timer 0, 1, 3, 4)
- Dual 32-bit general-purpose timer mode (Timer 0, 1, 3, 4)
- Watchdog timer mode (Timer 2)
Two possible clock sources:
- Internal clock
- External clock/event input via timer input pins (Timer 3)
Three possible operation modes:
- One-time operation (timer runs for one period then stops)
- Continuous operation (timer automatically resets after each period)
- Continuous operation with period reload (Timer 3)
Generates interrupts to the ARM CPU
Generates sync event to EDMA
Generates output event to device reset (Timer 2)
Generates output event to Real Timer Out (RTO) module (Timer 3)
External event capture via timer input pins (Timer 3)

For more detailed information, see the TMS320DM36x Digital Media System-on-Chip (DMSoC) Timer/Watchdog Timer User's Guide (SPRUFH0).

7.18.1 Timer Peripheral Register Description

Table 7-83 lists the Timer registers, their corresponding acronyms, and the device memory locations (offsets).

Table 7-83 Timer Global Registers

Offset	Acronym	Register Description
00h	PID12	Peripheral Identification Register 12
04h	EMUMGT	Emulation Management Register
10h	TIM12	Timer Counter Register 12
14h	TIM34	Timer Counter Register 34
18h	PRD12	Timer Period Register 12
1Ch	PRD34	Timer Period Register 34
20h	TCR	Timer Control Register
24h	TGCR	Timer Global Control Register
28h	WDTCR	Watchdog Timer Control Register
34h	REL12	Timer Reload Register 12
38h	REL34	Timer Reload Register 34
3Ch	CAP12	Timer Capture Register 12
40h	CAP34	Timer Capture Register 34
44h	INTCTL_STAT	Timer Interrupt Control and Status Register

7.18.2 Timer Electrical Data/Timing

Table 7-84 Timing Requirements for Timer Input⁽¹⁾ ⁽²⁾ (see Figure 7-54)

NO.			DEVICE		UNIT
NO.			MIN	MAX	UNIT
1	t_c(TIN)	Cycle time, TIM_IN	4P		ns
2	t_w(TINPH)	Pulse duration, TIM_IN high	0.45C	0.55C	ns
3	t_w(TINPL)	Pulse duration, TIM_IN low	0.45C	0.55C	ns
4	t_t(TIN)	Transition time, TIM_IN		5	ns

(1) GPIO001, GPIO002, GPIO003, and GPIO004 can be used as external clock inputs for Timer 3. See the TMS320DM36x Digital Media System-on-Chip (DMSoC) Timer/Watchdog Timer User's Guide (SPRUFH0).

(2) P = MXI1/CLKIN cycle time in ns. For example, when MXI1/CLKIN frequency is 24 MHz use P = 41.6 ns.

Figure 7-54 Timer Input Timing

7.19 Pulse Width Modulator (PWM)

The pulse width modulator (PWM) feature is very common in embedded systems. It provides a way to generate a pulse periodic waveform for motor control or can act as a digital-to-analog converter with some external components. This PWM peripheral is basically a timer with a period counter and a first-phase duration comparator, where bit width of the period and first-phase duration are both programmable. The Pulse Width Modulator (PWM) modules support the following features:

32-bit period counter
32-bit first-phase duration counter
8-bit repeat count for one-shot operation. One-shot operation will produce N + 1 periods of the waveform, where N is the repeat counter value.
Configurable to operate in either one-shot or continuous mode
Buffered period and first-phase duration registers
One-shot operation triggerable by hardware events with programmable edge transitions. (low-to-high or high-to-low).
One-shot operation triggerable by the ISIF VSYNC output of the video processing subsystem (VPSS), which allows any of the PWM instantiations to be used as a ISIF timer. This lets the device module to support the functions provided by the ISIF timer feature (generating strobe and shutter signals).
One-shot operation generates N+1 periods of waveform, N being the repeat count register value
Configurable PWM output pin inactive state
Interrupt and EDMA synchronization events

7.19.1 PWM Peripheral Register Description

Table 7-85 lists the PWM registers, their corresponding acronyms, and the device memory locations (offsets).

Table 7-85 Pulse Width Modulator (PWM) Registers

Offset	Acronym	Register Description
00h	PID	PWM Peripheral Identification Register
04h	PCR	PWM Peripheral Control Register
08h	CFG	PWM Configuration Register
0Ch	START	PWM Start Register
10h	RPT	PWM Repeat Count Register
14h	PER	PWM Period Register
18h	PH1D	PWM First-Phase Duration Register

7.19.2 PWM0/1/2/3 Electrical/Timing Data

Table 7-86 Switching Characteristics Over Recommended Operating Conditions for PWM0/1/2/3 Outputs⁽¹⁾ (see Figure 7-55 and Figure 7-56)

NO.	PARAMETER		DEVICE		UNIT
NO.	PARAMETER		MIN	MAX	UNIT
1	t_w(PWMH)	Pulse duration, PWMx high	37		ns
2	t_w(PWML)	Pulse duration, PWMx low	37		ns
3	t_t(PWM)	Transition time, PWMx		5	ns
4	t_d(ISIF-PWMV)	Delay time, ISIF(VD) trigger event to PWMx valid	0	10	ns

(1) P = MXI1/CLKIN cycle time in ns. For example, when MXI1/CLKIN frequency is 24 MHz use P = 41.6 ns.

Figure 7-55 PWM Output Timing

Figure 7-56 PWM Output Delay Timing

7.20 Real Time Out (RTO)

The device uses the Real Time Out (RTO) peripheral to provide appropriate input control signals to external devices such as motor controllers. This peripheral supports the following features:

Four separate outputs
Trigger on Timer3 event

7.20.1 Real Time Out (RTO) Peripheral Register Description

Table 7-87 lists the RTO registers, their corresponding acronyms, and the device memory locations (offsets).

Table 7-87 Real Time Out (RTO) Registers

Offset	Acronym	Register Description
0h	REVID	RTO Controller Revision ID Register
04h	CTRL_STATUS	RTO Controller Control and Status Register

7.20.2 RTO Electrical/Timing Data

Table 7-88 Switching Characteristics Over Recommended Operating Conditions for RTO Outputs (see Figure 7-57 and Figure 7-58)⁽¹⁾

NO.	PARAMETER		DEVICE		UNIT
NO.	PARAMETER		MIN	MAX	UNIT
1	t_w(RTOH)	Pulse duration, RTOx high	27.7	52.083	ns
2	t_w(RTOL)	Pulse duration, RTOx low	.45C	.55C	ns
3	t_t(RTO)	Transition time, RTOx	.45C	.55C	ns
4	t_{d(TIMER3-RTOV)}	Delay time, Timer 3 (TINT12 or TINT34) trigger event to RTOx valid		10	ns

(1) C = MXI1/CLKIN1 cycle time in ns. For example, when MXI1/CLKIN1 frequency is 24 MHz use C = 41.6 ns.

Figure 7-57 RTO Output Timing

Figure 7-58 RTO Output Delay Timing

7.21 Ethernet Media Access Controller (EMAC)

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and the network. The EMAC supports both 10Base-T (10 Mbits/second [Mbps]) and 100Base-TX (100 Mbps) in either half- or full-duplex mode. The EMAC module also supports hardware flow control and quality of service (QOS) support.

The frequencies supported for transmit and receive clocks are fixed by the IEEE 802.3 standard as:

2.5 MHz for 10Mbps
25 MHz for 100Mbps

The EMAC controls the flow of packet data from the device to the PHY. The MDIO module controls PHY configuration and status monitoring.

The EMAC module conforms to the IEEE 802.3-2002 standard, describing the “Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer” specifications. The IEEE 802.3 standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E).

Deviation from this standard, the EMAC module does not use the Transmit Coding Error signal MTXER. Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the EMAC will intentionally generate an incorrect checksum by inverting the frame CRC, so that the transmitted frame will be detected as an error by the network

Both the EMAC and the MDIO modules interface to the device through a custom interface that allows efficient data transmission and reception. This custom interface is referred to as the EMAC control module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to multiplex and control interrupts.

For more information, see the TMS320DM36x Digital Media System-on-Chip (DMSoC) Ethernet Media Access Controller (EMAC) User's Guide. (SPRUFI5).

7.21.1 EMAC Peripheral Register Description

Table 7-89 lists the EMAC registers, their corresponding acronyms, and the device memory locations (offsets).

Table 7-89 Ethernet Media Access Controller (EMAC) Control Module Registers

Slave VBUS Address Offset	Acronym	Register Description
0h	CMIDVER	Identification and Version Register
04h	CMSOFTRESET	Software Reset Register
08h	CMEMCONTROL	Emulation Control Register
Ch	CMINTCTRL	Interrupt Control Register
10h	CMRXTHRESHINTEN	Receive Threshold Interrupt Enable Register
14h	CMRXINTEN	Receive Interrupt Enable Register
18h	CMTXINTEN	Transmit Interrupt Enable Register
1Ch	CMMISCINTEN	Miscellaneous Interrupt Enable Register
40h	CMRXTHRESHINTSTAT	Receive Threshold Interrupt Status Register
44h	CMRXINTSTAT	Receive Interrupt Status Register
48h	CMTXINTSTAT	Transmit Interrupt Status Register
4Ch	CMMISCINTSTAT	Miscellaneous Interrupt Status Register
70Ch	CMRXINTMAX	Receive Interrupts Per Millisecond Register
74h	CMTXINTMAX	Transmit Interrupts Per Millisecond Register

Table 7-90 Ethernet Media Access Controller (EMAC) Registers

Offset	Acronym	Register Description
0h	TXIDVER	Transmit Identification and Version Register
4h	TXCONTROL	Transmit Control Register
8h	TXTEARDOWN	Transmit Teardown Register
10h	RXIDVER	Receive Identification and Version Register
14h	RXCONTROL	Receive Control Register
18h	RXTEARDOWN	Receive Teardown Register
80h	TXINTSTATRAW	Transmit Interrupt Status (Unmasked) Register
84h	TXINTSTATMASKED	Transmit Interrupt Status (Masked) Register
88h	TXINTMASKSET	Transmit Interrupt Mask Set Register
8Ch	TXINTMASKCLEAR	Transmit Interrupt Clear Register
90h	MACINVECTOR	MAC Input Vector Register
94h	MACEOIVECTOR	MAC End of Interrupt Vector Register
A0h	RXINTSTATRAW	Receive Interrupt Status (Unmasked) Register
A4h	RXINTSTATMASKED	Receive Interrupt Status (Masked) Register
A8h	RXINTMASKSET	Receive Interrupt Mask Set Register
ACh	RXINTMASKCLEAR	Receive Interrupt Mask Clear Register
B0h	MACINTSTATRAW	MAC Interrupt Status (Unmasked) Register
B4h	MACINTSTATMASKED	MAC Interrupt Status (Masked) Register
B8h	MACINTMASKSET	MAC Interrupt Mask Set Register
BCh	MACINTMASKCLEAR	MAC Interrupt Mask Clear Register
100h	RXMBPENABLE	Receive Multicast/Broadcast/Promiscuous Channel Enable Register
104h	RXUNICASTSET	Receive Unicast Enable Set Register
108h	RXUNICASTCLEAR	Receive Unicast Clear Register
10Ch	RXMAXLEN	Receive Maximum Length Register
110h	RXBUFFEROFFSET	Receive Buffer Offset Register
114h	RXFILTERLOWTHRESH	Receive Filter Low Priority Frame Threshold Register
120h	RX0FLOWTHRESH	Receive Channel 0 Flow Control Threshold Register
124h	RX1FLOWTHRESH	Receive Channel 1 Flow Control Threshold Register
128h	RX2FLOWTHRESH	Receive Channel 2 Flow Control Threshold Register
12Ch	RX3FLOWTHRESH	Receive Channel 3 Flow Control Threshold Register
130h	RX4FLOWTHRESH	Receive Channel 4 Flow Control Threshold Register
134h	RX5FLOWTHRESH	Receive Channel 5 Flow Control Threshold Register
138h	RX6FLOWTHRESH	Receive Channel 6 Flow Control Threshold Register
13Ch	RX7FLOWTHRESH	Receive Channel 7 Flow Control Threshold Register
140h	RX0FREEBUFFER	Receive Channel 0 Free Buffer Count Register
144h	RX1FREEBUFFER	Receive Channel 1 Free Buffer Count Register
148h	RX2FREEBUFFER	Receive Channel 2 Free Buffer Count Register
14Ch	RX3FREEBUFFER	Receive Channel 3 Free Buffer Count Register
150h	RX4FREEBUFFER	Receive Channel 4 Free Buffer Count Register
154h	RX5FREEBUFFER	Receive Channel 5 Free Buffer Count Register
158h	RX6FREEBUFFER	Receive Channel 6 Free Buffer Count Register
15Ch	RX7FREEBUFFER	Receive Channel 7 Free Buffer Count Register
160h	MACCONTROL	MAC Control Register
164h	MACSTATUS	MAC Status Register
168h	EMCONTROL	Emulation Control Register
16Ch	FIFOCONTROL	FIFO Control Register
170h	MACCONFIG	MAC Configuration Register
174h	SOFTRESET	Soft Reset Register
1D0h	MACSRCADDRLO	MAC Source Address Low Bytes Register
1D4h	MACSRCADDRHI	MAC Source Address High Bytes Register
1D8h	MACHASH1	MAC Hash Address Register 1
1DCh	MACHASH2	MAC Hash Address Register 2
1E0h	BOFFTEST	Back Off Test Register
1E4h	TPACETEST	Transmit Pacing Algorithm Test Register
1E8h	RXPAUSE	Receive Pause Timer Register
1ECh	TXPAUSE	Transmit Pause Timer Register
500h	MACADDRLO	MAC Address Low Bytes Register, Used in Receive Address Matching
504h	MACADDRHI	MAC Address High Bytes Register, Used in Receive Address Matching
508h	MACINDEX	MAC Index Register
600h	TX0HDP	Transmit Channel 0 DMA Head Descriptor Pointer Register
604h	TX1HDP	Transmit Channel 1 DMA Head Descriptor Pointer Register
608h	TX2HDP	Transmit Channel 2 DMA Head Descriptor Pointer Register
60Ch	TX3HDP	Transmit Channel 3 DMA Head Descriptor Pointer Register
610h	TX4HDP	Transmit Channel 4 DMA Head Descriptor Pointer Register
614h	TX5HDP	Transmit Channel 5 DMA Head Descriptor Pointer Register
618h	TX6HDP	Transmit Channel 6 DMA Head Descriptor Pointer Register
61Ch	TX7HDP	Transmit Channel 7 DMA Head Descriptor Pointer Register
620h	RX0HDP	Receive Channel 0 DMA Head Descriptor Pointer Register
624h	RX1HDP	Receive Channel 1 DMA Head Descriptor Pointer Register
628h	RX2HDP	Receive Channel 2 DMA Head Descriptor Pointer Register
62Ch	RX3HDP	Receive Channel 3 DMA Head Descriptor Pointer Register
630h	RX4HDP	Receive Channel 4 DMA Head Descriptor Pointer Register
634h	RX5HDP	Receive Channel 5 DMA Head Descriptor Pointer Register
638h	RX6HDP	Receive Channel 6 DMA Head Descriptor Pointer Register
63Ch	RX7HDP	Receive Channel 7 DMA Head Descriptor Pointer Register
640h	TX0CP	Transmit Channel 0 Completion Pointer Register
644h	TX1CP	Transmit Channel 1 Completion Pointer Register
648h	TX2CP	Transmit Channel 2 Completion Pointer Register
64Ch	TX3CP	Transmit Channel 3 Completion Pointer Register
650h	TX4CP	Transmit Channel 4 Completion Pointer Register
654h	TX5CP	Transmit Channel 5 Completion Pointer Register
658h	TX6CP	Transmit Channel 6 Completion Pointer Register
65Ch	TX7CP	Transmit Channel 7 Completion Pointer Register
660h	RX0CP	Receive Channel 0 Completion Pointer Register
664h	RX1CP	Receive Channel 1 Completion Pointer Register
668h	RX2CP	Receive Channel 2 Completion Pointer Register
66Ch	RX3CP	Receive Channel 3 Completion Pointer Register
670h	RX4CP	Receive Channel 4 Completion Pointer Register
674h	RX5CP	Receive Channel 5 Completion Pointer Register
678h	RX6CP	Receive Channel 6 Completion Pointer Register
67Ch	RX7CP	Receive Channel 7 Completion Pointer Register
Network Statistics Registers
200h	RXGOODFRAMES	Good Receive Frames Register
204h	RXBCASTFRAMES	Broadcast Receive Frames Register
208h	RXMCASTFRAMES	Multicast Receive Frames Register
20Ch	RXPAUSEFRAMES	Pause Receive Frames Register
210h	RXCRCERRORS	Receive CRC Errors Register
214h	RXALIGNCODEERRORS	Receive Alignment/Code Errors Register
218h	RXOVERSIZED	Receive Oversized Frames Register
21Ch	RXJABBER	Receive Jabber Frames Register
220h	RXUNDERSIZED	Receive Undersized Frames Register
224h	RXFRAGMENTS	Receive Frame Fragments Register
228h	RXFILTERED	Filtered Receive Frames Register
22Ch	RXQOSFILTERED	Receive QOS Filtered Frames Register
230h	RXOCTETS	Receive Octet Frames Register
234h	TXGOODFRAMES	Good Transmit Frames Register
238h	TXBCASTFRAMES	Broadcast Transmit Frames Register
23Ch	TXMCASTFRAMES	Multicast Transmit Frames Register
240h	TXPAUSEFRAMES	Pause Transmit Frames Register
244h	TXDEFERRED	Deferred Transmit Frames Register
248h	TXCOLLISION	Transmit Collision Frames Register
24Ch	TXSINGLECOLL	Transmit Single Collision Frames Register
250h	TXMULTICOLL	Transmit Multiple Collision Frames Register
254h	TXEXCESSIVECOLL	Transmit Excessive Collision Frames Register
258h	TXLATECOLL	Transmit Late Collision Frames Register
25Ch	TXUNDERRUN	Transmit Underrun Error Register
260h	TXCARRIERSENSE	Transmit Carrier Sense Errors Register
264h	TXOCTETS	Transmit Octet Frames Register
268h	FRAME64	Transmit and Receive 64 Octet Frames Register
26Ch	FRAME65T127	Transmit and Receive 65 to 127 Octet Frames Register
270h	FRAME128T255	Transmit and Receive 128 to 255 Octet Frames Register
274h	FRAME256T511	Transmit and Receive 256 to 511 Octet Frames Register
278h	FRAME512T1023	Transmit and Receive 512 to 1023 Octet Frames Register
27Ch	FRAME1024TUP	Transmit and Receive 1024 to RXMAXLEN Octet Frames Register
280h	NETOCTETS	Network Octet Frames Register
284h	RXSOFOVERRUNS	Receive FIFO or DMA Start of Frame Overruns Register
288h	RXMOFOVERRUNS	Receive FIFO or DMA Middle of Frame Overruns Register
28Ch	RXDMAOVERRUNS	Receive DMA Overruns Register

Table 7-91 EMAC Descriptor Memory

HEX ADDRESS RANGE	ACRONYM	DESCRIPTION
0x01D0 8000 - 0x01D0 9FFF	–	EMAC Control Module Descriptor Memory

7.21.2 Ethernet Media Access Controller (EMAC) Electrical Data/Timing

Table 7-92 Timing Requirements for MRCLK (see Figure 7-59)

NO.							UNIT
			10 Mbps		100 Mbps
			MIN	MAX	MIN	MAX
1	t_c(MRCLK)	Cycle time, MRCLK	400		40		ns
2	t_w(MRCLKH)	Pulse duration, MRCLK high	140		14		ns
3	t_w(MRCLKL)	Pulse duration, MRCLK low	140		14		ns

Figure 7-59 MRCLK Timing (EMAC - Receive)

Table 7-93 Timing Requirements for MTCLK (see Figure 7-59)

NO.							UNIT
			10 Mbps		100 Mbps
			MIN	MAX	MIN	MAX
1	t_c(MTCLK)	Cycle time, MTCLK	400		40		ns
2	t_w(MTCLKH)	Pulse duration, MTCLK high	140		14		ns
3	t_w(MTCLKL)	Pulse duration, MTCLK low	140		14		ns

Figure 7-60 MTCLK Timing (EMAC - Transmit)

Table 7-94 Timing Requirements for EMAC MII Receive 10/100 Mbit/s⁽¹⁾ (see Figure 7-61)

NO.					UNIT
NO.			MIN	MAX	UNIT
1	t_{su(MRXD-MRCLKH)}	Setup time, receive selected signals valid before MRCLK high	8		ns
2	t_{h(MRCLKH-MRXD)}	Hold time, receive selected signals valid after MRCLK high	8		ns

(1) Receive selected signals include: MRXD3-MRXD0, MRXDV, and MRXER.

Figure 7-61 EMAC Receive Interface Timing

Table 7-95 Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10/100 Mbit/s⁽¹⁾ (see Figure 7-62)

NO.					UNIT
NO.			MIN	MAX	UNIT
1	t_{d(MTCLKH-MTXD)}	Delay time, MTCLK high to transmit selected signals valid	5	25	ns

(1) Transmit selected signals include: MTXD3-MTXD0, and MTXEN.

Figure 7-62 EMAC Transmit Interface Timing

7.22 Management Data Input/Output (MDIO)

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system.

The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to interrogate and control Ethernet PHY using a shared two-wire bus. Host software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the negotiation results, and configure required parameters in the EMAC module for correct operation. The module is designed to allow almost transparent operation of the MDIO interface, with very little maintenance from the core processor. Only one PHY may be connected at any given time.

For more detailed information on the MDIO peripheral, see the TMS320DM36x Digital Media System-on-Chip (DMSoC) Ethernet Media Access Controller User's Guide (SPRUFI5).

7.22.1 MDIO Peripheral Register Description

Table 7-96 lists the MDIO registers, their corresponding acronyms, and the device memory locations (offsets).

Table 7-96 Management Data Input/Output (MDIO) Registers

Offset	Acronym	Register Description
0h	VERSION	Identification and Version Register
04h	CONTROL	MDIO Control Register
08h	ALIVE	PHY Alive Status register
Ch	LINK	PHY Link Status Register
10h	LINKINTRAW	MDIO Link Status Change Interrupt (Unmasked) Register
14h	LINKINTMASKED	MDIO Link Status Change Interrupt (Masked) Register
20h	USERINTRAW	MDIO User Command Complete Interrupt (Unmasked) Register
24h	USERINTMASKED	MDIO User Command Complete Interrupt (Masked) Register
28h	USERINTMASKSET	MDIO User Command Complete Interrupt Mask Set Register
2Ch	USERINTMASKCLEAR	MDIO User Command Complete Interrupt Mask Clear Register
80h	USERACCESS0	MDIO User Access Register 0
84h	USERPHYSEL0	MDIO User PHY Select Register 0
88h	USERACCESS1	MDIO User Access Register 1
8Ch	USERPHYSEL1	MDIO User PHY Select Register 1

7.22.2 Management Data Input/Output (MDIO) Electrical Data/Timing

Table 7-97 Timing Requirements for MDIO Input (see Figure 7-63 and Figure 7-64)

NO.			DEVICE		UNIT
NO.			MIN	MAX	UNIT
1	t_c(MDCLK)	Cycle time, MDCLK	400		ns
2	t_w(MDCLK)	Pulse duration, MDCLK high/low	180		ns
3	t_t(MDCLK)	Transition time, MDCLK		5	ns
4	t_{su(MDIO-MDCLKH)}	Setup time, MDIO data input valid before MDCLK high	10		ns
5	t_{h(MDCLKH-MDIO)}	Hold time, MDIO data input valid after MDCLK high	0		ns

Figure 7-63 MDIO Input Timing

Table 7-98 Switching Characteristics Over Recommended Operating Conditions for MDIO Output
(see Figure 7-64)

NO.			DEVICE		UNIT
NO.			MIN	MAX	UNIT
7	t_{d(MDCLKL-MDIO)}	Delay time, MDCLK low to MDIO data output valid		100	ns

Figure 7-64 MDIO Output Timing

7.23 Host-Port Interface (HPI) Peripheral

Note: HPI is pin multiplexed with Asynchronous EMIF at the output pin. HPI is available only when boot mode selected is HPI boot mode. In this configuration, the device will always act as a slave.

7.23.1 HPI Device-Specific Information

The device includes a user-configurable 16-bit Host-port interface (HPI16).

Multiplexed (address/data) operation
Configurable single full-word cycle and dual half-word cycle access modes
Bursting available utilizing 8-word read and write FIFOs
HPIA register supports auto-incrementing
HPID register/FIFOs providing data-path between external host interface and system bus
Multiple strobes and control signals to allow flexible host connection
Software control of data prefetching to the HPID/FIFOs
DMSoC-to-Host interrupt output signal controlled by HPIC accesses
Host-to-DMSoC interrupt controlled by HPIC accesses

NOTE: The device HPI does not support the HAS feature. For proper HPI operation if the HAS pin is routed out, the HAS pin must be pulled up via an external resistor.

The device HPICTL register (0x01C4 0024) is part of the System Module Registers. The HPICTL register controls write access to the HPI peripheral control and address registers and determines the host time-out value.

7.23.2 HPI Bus Master

The HPI peripheral includes a bus master interface that allows external device initiated transfers to access the DM369 system bus. See the Master Peripheral Mem Map column in Table 3-4, the device Memory Map.

7.23.3 HPI Peripheral Register Description

Table 7-99 lists the HPI registers, their corresponding acronyms, and the device memory locations (offsets).

Table 7-99 HPI Registers

Offset	Acronym	Register Description
0h	PID	Peripheral Identification Register
4h	PWREMU_MGMT	Power and Emulation Management Register
30h	HPIC	Host Port Interface Control Register
34h	HPIAW	Host Port Interface Write Address Register
38h	HPIAR	Host Port Interface Read Address Register

7.23.4 HPI Electrical Data/Timing

Table 7-100 Timing Requirements for Host-Port Interface Cycles⁽¹⁾ ⁽²⁾ (see Figure 7-65 and Figure 7-66)

NO.			DEVICE		UNIT
NO.			MIN	MAX	UNIT
1	t_{su(SELV-HSTBL)}	Setup time, select signals⁽³⁾ valid before HSTROBE low	6		ns
2	t_{h(HSTBL-SELV)}	Hold time, select signals⁽³⁾ valid after HSTROBE low	2		ns
3	t_w(HSTBL)	Pulse duration, HSTROBE active low	15		ns
4	t_w(HSTBH)	Pulse duration, HSTROBE inactive high between consecutive accesses	2P		ns
11	t_{su(HDV-HSTBH)}	Setup time, host data valid before HSTROBE high	5		ns
12	t_h(HSTBH-HDV)	Hold time, host data valid after HSTROBE high	2		ns
13	t_{h(HRDYL-HSTBL)}	Hold time, HSTROBE high after HRDY low. HSTROBE should not be inactivated until HRDY is active (low); otherwise, HPI writes will not complete properly.	2		ns

(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(2) P = PLLC1.SYSCLK4 period, where SYSCLK4 is an output clock of PLLC1. For more details, see Section 4.3, Device Clocking

(3) Select signals include: HCNTLA, HCNTLB, HR/W and HHWIL.

Table 7-101 Switching Characteristics for Host-Port Interface Cycles⁽¹⁾ ⁽²⁾ ⁽³⁾
(see Figure 7-65 and Figure 7-66)

NO.	PARAMETER			DEVICE		UNIT
NO.	PARAMETER			MIN	MAX	UNIT
5	t_{d(HSTBL-HRDYV)}	Delay time, HSTROBE low to HRDY valid	For HPI Write, HRDY can go high (not ready) for these HPI Write conditions; otherwise, HRDY stays low (ready): Case 1: Back-to-back HPIA writes (can be either first or second half-word) Case 2: HPIA write following a PREFETCH command (can be either first or second half-word) Case 3: HPID write when FIFO is full or flushing (can be either first or second half-word) Case 4: HPIA write and Write FIFO not empty For HPI Read, HRDY can go high (not ready) for these HPI Read conditions: Case 1: HPID read (with auto-increment) and data not in Read FIFO (can only happen to first half-word of HPID access) Case 2: First half-word access of HPID Read without auto-increment For HPI Read, HRDY stays low (ready) for these HPI Read conditions: Case 1: HPID read with auto-increment and data is already in Read FIFO (applies to either half-word of HPID access) Case 2: HPID read without auto-increment and data is already in Read FIFO (always applies to second half-word of HPID access) Case 3: HPIC or HPIA read (applies to either half-word access)		17	ns
6	t_{en(HSTBL-HDLZ)}	Enable time, HD driven from HSTROBE low		2		ns
7	t_d(HRDYL-HDV)	Delay time, HRDY low to HD valid			0	ns
8	t_{oh(HSTBH-HDV)}	Output hold time, HD valid after HSTROBE high		1.5		ns
14	t_{dis(HSTBH-HDV)}	Disable time, HD high-impedance from HSTROBE high			15	ns
15	t_d(HSTBL-HDV)	Delay time, HSTROBE low to HD valid	For HPI Read. Applies to conditions where data is already residing in HPID/FIFO: Case 1: HPIC or HPIA read Case 2: First half-word of HPID read with auto-increment and data is already in Read FIFO Case 3: Second half-word of HPID read with or without auto-increment		18	ns

(1) P = PLLC1.SYSCLK4 period, where SYSCLK4 is an output clock of PLLC1. For more details, see Section 3.3, Device Clocking.

(2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(3) By design, whenever HCS is driven inactive (high), HPI will drive HRDY active (low).

TMS320DM369 hpi16_read_timing_prs457UPDATED2.gif

Figure 7-65 HPI16 Read Timing (HAS Not Used, Tied High)

TMS320DM369 hpi16_write_timing_prs457updated2.gif

Figure 7-66 HPI16 Write Timing (HAS Not Used, Tied High)

7.24 Key Scan

The device contains Key Scan module that supports two types of Key Matrices - 4x4 and 5x3. It also supports the following features :

Supports the following two scan modes
- Channel Interval mode
- Scan Interval mode
Programmable key scan time
- Strobe time
- Interval time
Two input detection modes
- Direct mode
- 3-Data check mode
Supports one interrupt to detect the following:
- Key input changes
- Periodic time intervals after a key is pressed

7.24.1 Key Scan Peripheral Register Description

Section 7.24.1.1 lists the Key Scan registers, their corresponding acronyms, and the device memory locations (offsets).

7.24.1.1 Key Scan Registers

Offset	Register	Description
0x0	KEYCTRL	Module Control register
0x4	INTCENA	Interrupt Enable control
0x8	INTFLG	Interrupt Flag control
0xC	INTCLR	Interrupt Clear control
0x10	STRBWIDTH	Strobe width
0x14	INTERVALTIME	Interval Time
0x18	CONTITIME	Continuous timer
0x1C	CURRENTST	Keyscan current status
0x20	PREVIOUSST	Keyscan previous status
0x24	EMUCTRL	Emulation control

7.24.2 Key Scan Electrical Data/Timing

Table 7-102 Timing Requirements for Keyscan (see Figure 7-63 and Figure 7-64)

NO.			DEVICE		UNIT
NO.			MIN	MAX	UNIT
1	t_w(KEYOUTV)	Pulse duration, Keyscan out (active low mode)	(STWIDTH + 1)*CLK_P-1⁽¹⁾ ⁽²⁾		ns
2	t_w(KEYOUTL)	Pulse duration, Keyscan out (always out mode)	(STWIDTH + 1)*CLK_P-1⁽¹⁾ ⁽²⁾		ns
3	t_{su(KEYOUT-KEYIN)}	Setup time, Keyscan input (always out mode)	20		ns
3	t_{su(KEYOUT-KEYIN)}	Setup time, Keyscan input (active low mode)	20		ns
4	t_{h(KEYOUT-KEYIN)}	Hold time, Keyscan input (always out mode)	0		ns
4	t_{h(KEYOUT-KEYIN)}	Hold time, Keyscan input (active low mode)	0		ns

(1) STWIDTH = the value programmed into the STRBWIDTH register.

(2) CLK_P = 1/(PLLC1.AUXCLK/(DIV3+1)) or 1/(RTCXI), where RTCXI is the PRTCSS oscillator input pin frequency of 32.768kHz.

Figure 7-67 Key Scan Timing

7.25 Analog-to-Digital Converter (ADC)

The device has a 6-channel 10-bit Analog-to-Digital Converter (ADC) interface. The analog-to-digital converter (ADC) feature is very common in embedded systems. The following features are supported on the Analog-to-Digital Converter (ADC):

Six configurable analog input selects
Successive Approximation type 10 bit A-D converter
Programmable Sampling / Conversion Time (base clock is AUXCLK)
Channel select by Auto Scan conversion
Mode select by One-shot mode or Free-run mode
Programmable setup (idle) period to secure A/D sampling start time
Supports the clock stop signals to connect the PSC

For Analog-to-Digital Converter characteristics, see Table 6-2 and Section 6.1.

7.25.1 Analog-to-Digital Converter (ADC) Peripheral Register Description

Section 7.25.1.1 lists the ADC registers, their corresponding acronyms, and the device memory locations (offsets).

7.25.1.1 Analog-to-Digital Converter (ADC) Interface Registers

Offset	Register	Description
0x0	ADCTL	Control register
0x4	CMPTGT	Comparator target channel
0x8	CMPLDAT	Comparison A/D Lower data
0xC	CMPUDAT	Comparison A/D Upper data
0x10	SETDIV	SETUP divide value for start A/D conversion
0x14	CHSEL	Analog Input channel select
0x18	AD0DAT	A/D conversion data 0
0x1C	AD1DAT	A/D conversion data 1
0x20	AD2DAT	A/D conversion data 2
0x24	AD3DAT	A/D conversion data 3
0x28	AD4DAT	A/D conversion data 4
0x2C	AD5DAT	A/D conversion data 5
0x30	EMUCTRL	Emulation Control

7.26 Voice Codec

The device has Voice Codec with FIFO (Read FIFO/Write FIFO). The following features are supported on the Voice Codec module.

16bit x 16 word FIFO for Recording/Playback data transfer
Full differential Microphone Amplifier
Monaural single ended Line output
Monaural Speaker Amplifier (BTL)
Dynamic Range: 70dB(DAC)
Dynamic Range: 70dB(ADC)
200-300mW Speaker output at R_L = 8Ω
Sampling frequency: 8 KHz or 16 KHz
Automatic Level Control for Recording
Programmable Function by Register Control
- Digital Attenuator of DAC: 0 dB to -62 dB
- Digital gain control for Recording (0/ +6/ +12/ +18dB)
- Power Up/Down Control for each module
- 20 dB/26 dB Boost Selectable for Microphone Input
- Two Stage Notch filter

For Voice Codec characteristics, see Table 6-2 and Section 6.1.

7.26.1 Voice Codec Register Description

Section 7.26.1.1 lists the Voice Codec registers, their corresponding acronyms, and the device memory locations (offsets).

7.26.1.1 Voice Codec Registers

Offset	Register	Description
0x00	VC_PID	VCIF PID
0x04	VC_CTRL	VCIF Control Register
0x08	VC_INTEN	VCIF Interrupt enable
0x0C	VC_INTSTATUS	VCIF Interrupt status
0x10	VC_INTCLR	VCIF Interrupt status clear
0x14	VC_EMUL_CTRL	VCIF emulator Control
0x20	RFIFO	VCIF Read FIFO access register
0x24	WFIFO	VCIF Write FIFO access register
0x28	FIFOSTAT	FIFO Status
0x80	VC_REG00	Notch filter parameter 1
0x84	VC_REG01	Notch filter parameter 1
0x88	VC_REG02	Notch filter parameter 2
0x8C	VC_REG03	Notch filter parameter 2
0x90	VC_REG04	Recording side mode control
0x94	VC_REG05	PGM & MIC gain
0x98	VC_REG06	ALC
0xA4	VC_REG09	Digital soft mute/attention
0xA8	VC_REG10	Digital soft mute/attention
0xB0	VC_REG12	Power up/down control

7.27 IEEE 1149.1 JTAG

The JTAG ⁽¹⁾ interface is used for BSDL testing and emulation of the device.

(1)IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

The device requires that both TRST and RESET be asserted upon power up to be properly initialized. While RESET initializes the device, TRST initializes the device's emulation logic. Both resets are required for proper operation.

While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface and device's emulation logic in the reset state.

TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.

RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE correctly. Other boundary-scan instructions work correctly independent of current state of RESET.

For maximum reliability, the device includes an internal pulldown (PD) on the TRST pin to ensure that TRST will always be asserted upon power up and the device's internal emulation logic will always be properly initialized.

JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST.

When using this type of JTAG controller, assert TRST to initialize the device after power up and externally drive TRST high before attempting any emulation or boundary scan operations. Following the release of RESET, the low-to-high transition of TRST must be "seen" to latch the state of EMU1 and EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Emulation mode. For more detailed information, see the terminal functions section of this data sheet.

7.27.1 JTAG Register Description

Section 7.26.1.1 shows the DEVICE ID register (which includes the JTAG ID related information), its corresponding acronym, and the device memory location. For more details on the DEVICE ID register bit fields, see the TMS320DM36x Digital Media System-on-Chip (DMSoC) ARM Subsystem User's Guide (SPRUFG5).

Table 7-103 DEVICE ID Register

HEX ADDRESS RANGE	ACRONYM	REGISTER NAME	COMMENTS
0x01C4 0028	DEVICEID	JTAG Identification Register	Read-only. Provides 32-bit JTAG ID of the device.

The DEVICE ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the device, the DEVICE ID register resides at address location 0x01C4 0028. The register hex value for the device is: 0xXB70 002F where 'X' denotes the silicon revision of the device. For more details on the silicon revision, see theTMS320DM369 Digital Media System-on-Chip (DMSoC), Silicon Revision 1.2, Silicon Errata (SPRZ441).

7.27.2 JTAG Test-Port Electrical Data/Timing

Table 7-104 Timing Requirements for JTAG Test Port (see Figure 7-68)

NO.			DEVICE		UNIT
NO.			MIN	MAX	UNIT
1	t_c(TCK)	Cycle time, TCK	50		ns
2	tw(TCKH)	Pulse duration, TCK high	20		ns
3	tw(TCKL)	Pulse duration, TCK low	20		ns
4	t_{su(TDIV-RTCKH)}	Setup time, TDI valid before RTCK high	5		ns
5	t_{h(RTCKH-TDIIV)}	Hold time, TDI valid after RTCK high	10		ns
6	t_{su(TMSV-RTCKH)}	Setup time, TMS valid before RTCK high	5		ns
7	t_{h(RTCKH-TMSV)}	Hold time, TMS valid after RTCK high	10		ns

Figure 7-68 JTAG Input Timing

Table 7-105 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 7-68)

NO.	PARAMETER		DEVICE		UNIT
NO.	PARAMETER		MIN	MAX	UNIT
8	t_c(RTCK)	Cycle time, RTCK	50		ns
9	tw(RTCKH)	Pulse duration, RTCK high	20		ns
10	tw(RTCKL)	Pulse duration, RTCK low	20		ns
11	t_{r(all JTAG outputs)}	Rise time, all JTAG outputs		5	ns
12	t_{f(all JTAG outputs)}	Fall time, all JTAG outputs		5	ns
13	t_{d(RTCKL-TDOV)}	Delay time, TCK low to TDO valid	0	23	ns

Figure 7-69 JTAG Output Timing

Package Options

Mechanical Data (Package|Pins)

Thermal pad, mechanical data (Package|Pins)

Orderable Information

7 Peripheral Information and Electrical Specifications

7.1 Parameter Information Device-Specific Information

7.1.1 Signal Transition Levels

7.1.2 Timing Parameters and Board Routing Analysis

7.2 Recommended Clock and Control Signal Transition Behavior

7.3 Power Supplies

Table 7-1 Power Supplies

7.4 Power-Supply Sequencing

7.4.1 Simple Power-On and Power-Off Method

7.4.2 Restricted Power-On and Power-Off Method

7.4.3 Power-Supply Design Considerations

7.4.4 Power-Supply Decoupling

7.5 Reset

7.5.1 Reset Electrical Data/Timing

Table 7-2 Timing Requirements for Reset (1) (2) (3) (see Figure 7-4)

7.6 Oscillators and Clocks

7.6.1 MXI1 Oscillator

Table 7-3 Switching Characteristics Over Recommended Operating Conditions for System Oscillator

7.6.2 Clock PLL Electrical Data/Timing (Input and Output Clocks)

Table 7-4 Timing Requirements for MXI1/CLKIN1(1)(2)(3) (see Figure 7-6)

Table 7-5 Switching Characteristics Over Recommended Operating Conditions for CLKOUT0/CLKOUT1(1) (2) (see Figure 7-7)

Table 7-6 Switching Characteristics Over Recommended Operating Conditions for CLKOUT2(1) (2) (see Figure 7-8)

7.6.3 PRTCSS Oscillator

7.6.4 PRTCSS Electrical Data/Timing

Table 7-7 Timing Requirements for RTCXI(1) (2) (see Figure 7-6)

Table 7-8 Switching Characteristics Over Recommended Operating Conditions for RTC Oscillator

7.7 Power Management and Real Time Clock Subsystem (PRTCSS)

7.7.1 PRTCSS Peripheral Register Description

Table 7-9 PRTC Interface (PRTCIF) Registers

Table 7-10 Power Management and Real Time Clock Subsystem (PRTCSS) Registers

7.8 General-Purpose Input/Output (GPIO)

Table 7-11 GPIO Pin Voltage Level and Power Supply Reference

7.8.1 GPIO Peripheral Register Description

Table 7-12 General-Purpose Input/Output (GPIO) Registers

7.8.2 GPIO Peripheral Input/Output Electrical Data/Timing

Table 7-13 Timing Requirements for GPIO Inputs (see Figure 7-11)

Table 7-14 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see Figure 7-11)

7.8.3 GPIO Peripheral External Interrupts Electrical Data/Timing

Table 7-15 Timing Requirements for External Interrupts/EDMA Events(1) (see Figure 7-12)

7.9 EDMA Controller

7.9.1 EDMA Channel Synchronization Events

Table 7-16 EDMA Channel Synchronization Events(1) (2)

7.9.2 EDMA Peripheral Register Description

Table 7-17 EDMA Registers

Table 7-18 EDMA Parameter Set RAM

Table 7-19 Parameter Set Entries

7.10 External Memory Interface (EMIF)

7.10.1 Asynchronous EMIF (AEMIF)

7.10.1.1 NAND (NAND, SmartMedia, xD)

7.10.1.2 OneNAND

7.10.1.3 EMIF Peripheral Register Descriptions

Table 7-20 External Memory Interface (EMIF) Registers

7.10.1.4 AEMIF Electrical Data/Timing

Table 7-21 Timing Requirements for Asynchronous Memory Cycles for AEMIF Module(1) (see Figure 7-13 and Figure 7-14)

Table 7-22 Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for AEMIF Module(1) (2) (3) (see Figure 7-13 and Figure 7-14)

7.10.2 DDR2/mDDR Memory Controller

7.10.3 DDR2/mDDR Memory Controller Electrical Data/Timing

Table 7-23 Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory Controller(1) (2)(see Figure 7-18)

7.10.3.1 DDR2/mDDR Routing Specifications

7.10.3.1.1 DDR2/mDDR Interface

7.10.3.1.2 DDR2/mDDR Interface Schematic

7.10.3.1.3 Compatible JEDEC DDR2/mDDR Devices

Table 7-24 Compatible JEDEC DDR2/mDDR Devices

7.10.3.1.4 PCB Stack Up

Table 7-25 Minimum PCB Stack Up

Table 7-26 PCB Stack Up Specifications(3)

7.10.3.1.5 Placement

Table 7-27 Placement Specifications

7.10.3.1.6 DDR2/mDDR Keep Out Region

7.10.3.1.7 Bulk Bypass Capacitors

Table 7-28 Bulk Bypass Capacitors

7.10.3.1.8 High-Speed Bypass Capacitors

Table 7-29 High-Speed Bypass Capacitors

7.10.3.1.9 Net Classes

Table 7-30 Clock Net Class Definitions

Table 7-31 Signal Net Class Definitions

Table 7-2 Timing Requirements for Reset ⁽¹⁾ ⁽²⁾ ⁽³⁾ (see Figure 7-4)

Table 7-4 Timing Requirements for MXI1/CLKIN1⁽¹⁾⁽²⁾⁽³⁾ (see Figure 7-6)

Table 7-5 Switching Characteristics Over Recommended Operating Conditions for CLKOUT0/CLKOUT1⁽¹⁾ ⁽²⁾ (see Figure 7-7)

Table 7-6 Switching Characteristics Over Recommended Operating Conditions for CLKOUT2⁽¹⁾ ⁽²⁾ (see Figure 7-8)

Table 7-7 Timing Requirements for RTCXI⁽¹⁾ ⁽²⁾ (see Figure 7-6)

Table 7-14 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 7-11)

Table 7-15 Timing Requirements for External Interrupts/EDMA Events⁽¹⁾ (see Figure 7-12)

Table 7-16 EDMA Channel Synchronization Events⁽¹⁾ ⁽²⁾

Table 7-21 Timing Requirements for Asynchronous Memory Cycles for AEMIF Module⁽¹⁾ (see Figure 7-13 and Figure 7-14)

Table 7-22 Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for AEMIF Module⁽¹⁾ ⁽²⁾ ⁽³⁾ (see Figure 7-13 and Figure 7-14)

Table 7-23 Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory Controller⁽¹⁾ ⁽²⁾(see Figure 7-18)

Table 7-26 PCB Stack Up Specifications⁽³⁾

Table 7-33 CK and ADDR_CTRL Routing Specification ⁽¹⁾

Table 7-37 Timing Requirements for MMC/SD Module
(see Figure 7-28 and Figure 7-30)

Table 7-45 Timing Requirements for VPFE PCLK Master/Slave Mode⁽¹⁾ (see Figure 7-31)

Table 7-47 Timing Requirements for VPFE (ISIF) Master Mode⁽¹⁾ (see Figure 7-33)

Table 7-53 Timing Requirements for VPBE Control Input With Respect to PCLK and EXTCLK⁽¹⁾ ⁽³⁾ ⁽²⁾ (see Figure 7-36)

Table 7-54 Switching Characteristics Over Recommended Operating Conditions for VPBE Control and Data Output With Respect to PCLK and EXTCLK⁽¹⁾ ⁽²⁾ ⁽³⁾ (see Figure 7-37)

Table 7-55 Switching Characteristics Over Recommended Operating Conditions for VPBE Control and Data Output With Respect to VCLK⁽¹⁾ ⁽²⁾ ⁽³⁾(see Figure 7-38)

Table 7-59 Timing Requirements for UARTx Receive (see Figure 7-42)⁽¹⁾

Table 7-60 Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit
(see Figure 7-42)⁽¹⁾

Table 7-62 General Switching Characteristics in Master Mode⁽¹⁾

Table 7-64 General Switching Characteristics in Slave Mode (For 3- and4-Pin Modes)⁽¹⁾

Table 7-65 General Input Timing Requirements in Slave Mode⁽¹⁾

Table 7-67 Additional Output Switching Characteristics of 4-Pin Chip-Select Option in Slave Mode⁽¹⁾